Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)
* Implement SMULWB, SMULWT, SMLAWB, SMLAWT, and add tests for some multiply instructions * Improve test descriptions * Rename SMULH to SMUL__ * Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions * Fix new tests * Replace AND 0xFFFF with 16-bits zero extension (more efficient)
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12 changed files with 666 additions and 195 deletions
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@ -11,6 +11,26 @@ namespace Ryujinx.Tests.Cpu
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#if Alu32
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#region "ValueSource (Opcodes)"
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private static uint[] _Ssat_Usat_()
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{
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return new uint[]
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{
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0xe6a00010u, // SSAT R0, #1, R0, LSL #0
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0xe6a00050u, // SSAT R0, #1, R0, ASR #32
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0xe6e00010u, // USAT R0, #0, R0, LSL #0
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0xe6e00050u // USAT R0, #0, R0, ASR #32
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};
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}
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private static uint[] _Ssat16_Usat16_()
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{
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return new uint[]
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{
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0xe6a00f30u, // SSAT16 R0, #1, R0
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0xe6e00f30u, // USAT16 R0, #0, R0
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};
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}
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private static uint[] _Lsr_Lsl_Asr_Ror_()
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{
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return new uint[]
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@ -56,6 +76,41 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Ssat_Usat([ValueSource("_Ssat_Usat_")] uint opcode,
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[Values(0u, 0xdu)] uint rd,
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[Values(1u, 0xdu)] uint rn,
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[Values(0u, 7u, 8u, 0xfu, 0x10u, 0x1fu)] uint sat,
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[Values(0u, 7u, 8u, 0xfu, 0x10u, 0x1fu)] uint shift,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
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{
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opcode |= ((rn & 15) << 0) | ((shift & 31) << 7) | ((rd & 15) << 12) | ((sat & 31) << 16);
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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SingleOpcode(opcode, r1: wn, sp: w31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Ssat16_Usat16([ValueSource("_Ssat16_Usat16_")] uint opcode,
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[Values(0u, 0xdu)] uint rd,
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[Values(1u, 0xdu)] uint rn,
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[Values(0u, 7u, 8u, 0xfu)] uint sat,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
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{
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opcode |= ((rn & 15) << 0) | ((rd & 15) << 12) | ((sat & 15) << 16);
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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SingleOpcode(opcode, r1: wn, sp: w31);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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