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Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)

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* Implement SMULWB, SMULWT, SMLAWB, SMLAWT, and add tests for some multiply instructions

* Improve test descriptions

* Rename SMULH to SMUL__

* Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions

* Fix new tests

* Replace AND 0xFFFF with 16-bits zero extension (more efficient)
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gdkchan 2020-02-29 17:51:55 -03:00 • committed by GitHub
parent b8ee5b15ab
commit fb0939f9b6
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12 changed files with 666 additions and 195 deletions
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28
Ryujinx.Tests.Unicorn/UnicornAArch32.cs
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@ -45,10 +45,10 @@ namespace Ryujinx.Tests.Unicorn
set => SetRegister(Arm32Register.PC, value);
}
public uint APSR
public uint CPSR
{
get => (uint)GetRegister(Arm32Register.APSR);
set => SetRegister(Arm32Register.APSR, (uint)value);
get => (uint)GetRegister(Arm32Register.CPSR);
set => SetRegister(Arm32Register.CPSR, (uint)value);
}
public int Fpscr
@ -57,28 +57,34 @@ namespace Ryujinx.Tests.Unicorn
set => SetRegister(Arm32Register.FPSCR, (uint)value);
}
public bool QFlag
{
get => (CPSR & 0x8000000u) != 0;
set => CPSR = (CPSR & ~0x8000000u) | (value ? 0x8000000u : 0u);
}
public bool OverflowFlag
{
get => (APSR & 0x10000000u) != 0;
set => APSR = (APSR & ~0x10000000u) | (value ? 0x10000000u : 0u);
get => (CPSR & 0x10000000u) != 0;
set => CPSR = (CPSR & ~0x10000000u) | (value ? 0x10000000u : 0u);
}
public bool CarryFlag
{
get => (APSR & 0x20000000u) != 0;
set => APSR = (APSR & ~0x20000000u) | (value ? 0x20000000u : 0u);
get => (CPSR & 0x20000000u) != 0;
set => CPSR = (CPSR & ~0x20000000u) | (value ? 0x20000000u : 0u);
}
public bool ZeroFlag
{
get => (APSR & 0x40000000u) != 0;
set => APSR = (APSR & ~0x40000000u) | (value ? 0x40000000u : 0u);
get => (CPSR & 0x40000000u) != 0;
set => CPSR = (CPSR & ~0x40000000u) | (value ? 0x40000000u : 0u);
}
public bool NegativeFlag
{
get => (APSR & 0x80000000u) != 0;
set => APSR = (APSR & ~0x80000000u) | (value ? 0x80000000u : 0u);
get => (CPSR & 0x80000000u) != 0;
set => CPSR = (CPSR & ~0x80000000u) | (value ? 0x80000000u : 0u);
}
public UnicornAArch32()