Core timing 2.0 (#4913)

* Core::Timing: Add multiple timer, one for each core

* revert clang-format; work on tests for CoreTiming

* Kernel:: Add support for multiple cores, asserts in HandleSyncRequest because Thread->status == WaitIPC

* Add some TRACE_LOGs

* fix tests

* make some adjustments to qt-debugger, cheats and gdbstub(probably still broken)

* Make ARM_Interface::id private, rework ARM_Interface ctor

* ReRename TimingManager to Timing for smaler diff

* addressed review comments
This commit is contained in:
Ben 2020-02-21 19:31:32 +01:00 committed by GitHub
parent e3dbdcbdff
commit 55ec7031cc
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32 changed files with 760 additions and 535 deletions

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@ -35,7 +35,7 @@ static inline std::enable_if_t<std::is_integral_v<T>> WriteOp(const GatewayCheat
Core::System& system) {
u32 addr = line.address + state.offset;
write_func(addr, static_cast<T>(line.value));
system.CPU().InvalidateCacheRange(addr, sizeof(T));
system.InvalidateCacheRange(addr, sizeof(T));
}
template <typename T, typename ReadFunction, typename CompareFunc>
@ -105,7 +105,7 @@ static inline std::enable_if_t<std::is_integral_v<T>> IncrementiveWriteOp(
Core::System& system) {
u32 addr = line.value + state.offset;
write_func(addr, static_cast<T>(state.reg));
system.CPU().InvalidateCacheRange(addr, sizeof(T));
system.InvalidateCacheRange(addr, sizeof(T));
state.offset += sizeof(T);
}
@ -143,7 +143,8 @@ static inline void PatchOp(const GatewayCheat::CheatLine& line, State& state, Co
}
u32 num_bytes = line.value;
u32 addr = line.address + state.offset;
system.CPU().InvalidateCacheRange(addr, num_bytes);
system.InvalidateCacheRange(addr, num_bytes);
bool first = true;
u32 bit_offset = 0;
if (num_bytes > 0)