Core timing 2.0 (#4913)
* Core::Timing: Add multiple timer, one for each core * revert clang-format; work on tests for CoreTiming * Kernel:: Add support for multiple cores, asserts in HandleSyncRequest because Thread->status == WaitIPC * Add some TRACE_LOGs * fix tests * make some adjustments to qt-debugger, cheats and gdbstub(probably still broken) * Make ARM_Interface::id private, rework ARM_Interface ctor * ReRename TimingManager to Timing for smaler diff * addressed review comments
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32 changed files with 760 additions and 535 deletions
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@ -35,7 +35,7 @@ static inline std::enable_if_t<std::is_integral_v<T>> WriteOp(const GatewayCheat
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Core::System& system) {
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u32 addr = line.address + state.offset;
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write_func(addr, static_cast<T>(line.value));
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system.CPU().InvalidateCacheRange(addr, sizeof(T));
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system.InvalidateCacheRange(addr, sizeof(T));
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}
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template <typename T, typename ReadFunction, typename CompareFunc>
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@ -105,7 +105,7 @@ static inline std::enable_if_t<std::is_integral_v<T>> IncrementiveWriteOp(
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Core::System& system) {
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u32 addr = line.value + state.offset;
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write_func(addr, static_cast<T>(state.reg));
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system.CPU().InvalidateCacheRange(addr, sizeof(T));
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system.InvalidateCacheRange(addr, sizeof(T));
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state.offset += sizeof(T);
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}
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@ -143,7 +143,8 @@ static inline void PatchOp(const GatewayCheat::CheatLine& line, State& state, Co
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}
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u32 num_bytes = line.value;
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u32 addr = line.address + state.offset;
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system.CPU().InvalidateCacheRange(addr, num_bytes);
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system.InvalidateCacheRange(addr, num_bytes);
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bool first = true;
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u32 bit_offset = 0;
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if (num_bytes > 0)
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