Core timing 2.0 (#4913)
* Core::Timing: Add multiple timer, one for each core * revert clang-format; work on tests for CoreTiming * Kernel:: Add support for multiple cores, asserts in HandleSyncRequest because Thread->status == WaitIPC * Add some TRACE_LOGs * fix tests * make some adjustments to qt-debugger, cheats and gdbstub(probably still broken) * Make ARM_Interface::id private, rework ARM_Interface ctor * ReRename TimingManager to Timing for smaler diff * addressed review comments
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@ -46,7 +46,9 @@ void RPCServer::HandleWriteMemory(Packet& packet, u32 address, const u8* data, u
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Core::System::GetInstance().Memory().WriteBlock(
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*Core::System::GetInstance().Kernel().GetCurrentProcess(), address, data, data_size);
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// If the memory happens to be executable code, make sure the changes become visible
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Core::CPU().InvalidateCacheRange(address, data_size);
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// Is current core correct here?
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Core::System::GetInstance().InvalidateCacheRange(address, data_size);
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}
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packet.SetPacketDataSize(0);
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packet.SendReply();
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