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core/arm: Improve timing accuracy before service calls in JIT

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We also correct the CPU JIT's implementation of Step.
This commit is contained in:
MerryMage 2017-12-03 02:57:08 +00:00
parent dc030c78c3
commit 7cd8b437aa
9 changed files with 59 additions and 53 deletions
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42
src/core/arm/dynarmic/arm_dynarmic.cpp
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@ -40,11 +40,20 @@ static bool IsReadOnlyMemory(u32 vaddr) {
return false;
}
static void AddTicks(u64 ticks) {
CoreTiming::AddTicks(ticks);
}
static u64 GetTicksRemaining() {
int ticks = CoreTiming::GetDowncount();
return static_cast<u64>(ticks <= 0 ? 0 : ticks);
}
static Dynarmic::UserCallbacks GetUserCallbacks(
const std::shared_ptr<ARMul_State>& interpeter_state, Memory::PageTable* current_page_table) {
const std::shared_ptr<ARMul_State>& interpreter_state, Memory::PageTable* current_page_table) {
Dynarmic::UserCallbacks user_callbacks{};
user_callbacks.InterpreterFallback = &InterpreterFallback;
user_callbacks.user_arg = static_cast<void*>(interpeter_state.get());
user_callbacks.user_arg = static_cast<void*>(interpreter_state.get());
user_callbacks.CallSVC = &SVC::CallSVC;
user_callbacks.memory.IsReadOnlyMemory = &IsReadOnlyMemory;
user_callbacks.memory.ReadCode = &Memory::Read32;
@ -56,8 +65,10 @@ static Dynarmic::UserCallbacks GetUserCallbacks(
user_callbacks.memory.Write16 = &Memory::Write16;
user_callbacks.memory.Write32 = &Memory::Write32;
user_callbacks.memory.Write64 = &Memory::Write64;
user_callbacks.AddTicks = &AddTicks;
user_callbacks.GetTicksRemaining = &GetTicksRemaining;
user_callbacks.page_table = &current_page_table->pointers;
user_callbacks.coprocessors[15] = std::make_shared<DynarmicCP15>(interpeter_state);
user_callbacks.coprocessors[15] = std::make_shared<DynarmicCP15>(interpreter_state);
return user_callbacks;
}
@ -66,6 +77,19 @@ ARM_Dynarmic::ARM_Dynarmic(PrivilegeMode initial_mode) {
PageTableChanged();
}
MICROPROFILE_DEFINE(ARM_Jit, "ARM JIT", "ARM JIT", MP_RGB(255, 64, 64));
void ARM_Dynarmic::Run() {
ASSERT(Memory::GetCurrentPageTable() == current_page_table);
MICROPROFILE_SCOPE(ARM_Jit);
jit->Run(GetTicksRemaining());
}
void ARM_Dynarmic::Step() {
InterpreterFallback(jit->Regs()[15], jit, static_cast<void*>(interpreter_state.get()));
}
void ARM_Dynarmic::SetPC(u32 pc) {
jit->Regs()[15] = pc;
}
@ -124,17 +148,6 @@ void ARM_Dynarmic::SetCP15Register(CP15Register reg, u32 value) {
interpreter_state->CP15[reg] = value;
}
MICROPROFILE_DEFINE(ARM_Jit, "ARM JIT", "ARM JIT", MP_RGB(255, 64, 64));
void ARM_Dynarmic::ExecuteInstructions(int num_instructions) {
ASSERT(Memory::GetCurrentPageTable() == current_page_table);
MICROPROFILE_SCOPE(ARM_Jit);
std::size_t ticks_executed = jit->Run(static_cast<unsigned>(num_instructions));
CoreTiming::AddTicks(ticks_executed);
}
void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
memcpy(ctx.cpu_registers, jit->Regs().data(), sizeof(ctx.cpu_registers));
memcpy(ctx.fpu_registers, jit->ExtRegs().data(), sizeof(ctx.fpu_registers));
@ -168,6 +181,7 @@ void ARM_Dynarmic::PrepareReschedule() {
}
void ARM_Dynarmic::ClearInstructionCache() {
// TODO: Clear interpreter cache when appropriate.
for (const auto& j : jits) {
j.second->ClearCache();
}

4
src/core/arm/dynarmic/arm_dynarmic.h
View file

@ -19,6 +19,9 @@ class ARM_Dynarmic final : public ARM_Interface {
public:
ARM_Dynarmic(PrivilegeMode initial_mode);
void Run() override;
void Step() override;
void SetPC(u32 pc) override;
u32 GetPC() const override;
u32 GetReg(int index) const override;
@ -36,7 +39,6 @@ public:
void LoadContext(const ThreadContext& ctx) override;
void PrepareReschedule() override;
void ExecuteInstructions(int num_instructions) override;
void ClearInstructionCache() override;
void PageTableChanged() override;