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core/arm: Improve timing accuracy before service calls in JIT

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We also correct the CPU JIT's implementation of Step.
This commit is contained in:
MerryMage 2017-12-03 02:57:08 +00:00
parent dc030c78c3
commit 7cd8b437aa
9 changed files with 59 additions and 53 deletions
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13
src/core/arm/dyncom/arm_dyncom.cpp
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@ -2,6 +2,7 @@
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include <algorithm>
#include <cstring>
#include <memory>
#include "core/arm/dyncom/arm_dyncom.h"
@ -20,6 +21,14 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
ARM_DynCom::~ARM_DynCom() {}
void ARM_DynCom::Run() {
ExecuteInstructions(std::max(CoreTiming::GetDowncount(), 0));
}
void ARM_DynCom::Step() {
ExecuteInstructions(1);
}
void ARM_DynCom::ClearInstructionCache() {
state->instruction_cache.clear();
trans_cache_buf_top = 0;
@ -79,10 +88,6 @@ void ARM_DynCom::SetCP15Register(CP15Register reg, u32 value) {
void ARM_DynCom::ExecuteInstructions(int num_instructions) {
state->NumInstrsToExecute = num_instructions;
// Dyncom only breaks on instruction dispatch. This only happens on every instruction when
// executing one instruction at a time. Otherwise, if a block is being executed, more
// instructions may actually be executed than specified.
unsigned ticks_executed = InterpreterMainLoop(state.get());
CoreTiming::AddTicks(ticks_executed);
}

6
src/core/arm/dyncom/arm_dyncom.h
View file

@ -15,6 +15,9 @@ public:
ARM_DynCom(PrivilegeMode initial_mode);
~ARM_DynCom();
void Run() override;
void Step() override;
void ClearInstructionCache() override;
void PageTableChanged() override;
@ -35,8 +38,9 @@ public:
void LoadContext(const ThreadContext& ctx) override;
void PrepareReschedule() override;
void ExecuteInstructions(int num_instructions) override;
private:
void ExecuteInstructions(int num_instructions);
std::unique_ptr<ARMul_State> state;
};