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Prefix all size_t with std::

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done automatically by executing regex replace `([^:0-9a-zA-Z_])size_t([^0-9a-zA-Z_])` -> `$1std::size_t$2`
This commit is contained in:
Weiyi Wang 2018-09-06 16:03:28 -04:00
parent eca98eeb3e
commit 7d8f115185
158 changed files with 669 additions and 634 deletions
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10
src/core/arm/dyncom/arm_dyncom.cpp
View file

@ -27,10 +27,10 @@ public:
fpexc = 0;
}
u32 GetCpuRegister(size_t index) const override {
u32 GetCpuRegister(std::size_t index) const override {
return cpu_registers[index];
}
void SetCpuRegister(size_t index, u32 value) override {
void SetCpuRegister(std::size_t index, u32 value) override {
cpu_registers[index] = value;
}
u32 GetCpsr() const override {
@ -39,10 +39,10 @@ public:
void SetCpsr(u32 value) override {
cpsr = value;
}
u32 GetFpuRegister(size_t index) const override {
u32 GetFpuRegister(std::size_t index) const override {
return fpu_registers[index];
}
void SetFpuRegister(size_t index, u32 value) override {
void SetFpuRegister(std::size_t index, u32 value) override {
fpu_registers[index] = value;
}
u32 GetFpscr() const override {
@ -87,7 +87,7 @@ void ARM_DynCom::ClearInstructionCache() {
trans_cache_buf_top = 0;
}
void ARM_DynCom::InvalidateCacheRange(u32, size_t) {
void ARM_DynCom::InvalidateCacheRange(u32, std::size_t) {
ClearInstructionCache();
}

2
src/core/arm/dyncom/arm_dyncom.h
View file

@ -19,7 +19,7 @@ public:
void Step() override;
void ClearInstructionCache() override;
void InvalidateCacheRange(u32 start_address, size_t length) override;
void InvalidateCacheRange(u32 start_address, std::size_t length) override;
void PageTableChanged() override;
void SetPC(u32 pc) override;

2
src/core/arm/dyncom/arm_dyncom_thumb.cpp
View file

@ -293,7 +293,7 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3
0xE6FF0FB0, // REVSH
};
size_t subset_index = BITS(tinstr, 6, 7);
std::size_t subset_index = BITS(tinstr, 6, 7);
if (subset_index == 2) {
valid = ThumbDecodeStatus::UNDEFINED;

6
src/core/arm/dyncom/arm_dyncom_trans.cpp
View file

@ -9,8 +9,8 @@
char trans_cache_buf[TRANS_CACHE_SIZE];
size_t trans_cache_buf_top = 0;
static void* AllocBuffer(size_t size) {
size_t start = trans_cache_buf_top;
static void* AllocBuffer(std::size_t size) {
std::size_t start = trans_cache_buf_top;
trans_cache_buf_top += size;
ASSERT_MSG(trans_cache_buf_top <= TRANS_CACHE_SIZE, "Translation cache is full!");
return static_cast<void*>(&trans_cache_buf[start]);
@ -2015,4 +2015,4 @@ const transop_fp_t arm_instruction_trans[] = {
INTERPRETER_TRANSLATE(blx_1_thumb),
};
const size_t arm_instruction_trans_len = sizeof(arm_instruction_trans) / sizeof(transop_fp_t);
const std::size_t arm_instruction_trans_len = sizeof(arm_instruction_trans) / sizeof(transop_fp_t);

4
src/core/arm/dyncom/arm_dyncom_trans.h
View file

@ -491,8 +491,8 @@ typedef arm_inst* ARM_INST_PTR;
typedef ARM_INST_PTR (*transop_fp_t)(unsigned int, int);
extern const transop_fp_t arm_instruction_trans[];
extern const size_t arm_instruction_trans_len;
extern const std::size_t arm_instruction_trans_len;
#define TRANS_CACHE_SIZE (64 * 1024 * 2000)
extern char trans_cache_buf[TRANS_CACHE_SIZE];
extern size_t trans_cache_buf_top;
extern std::size_t trans_cache_buf_top;