VideoCore: Split texturing regs from Regs struct
This commit is contained in:
Yuri Kunde Schlesner
parent
000e78144c
commit
9017093f58
17 changed files with 548 additions and 507 deletions
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@ -19,6 +19,7 @@
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#include "common/logging/log.h"
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#include "common/vector_math.h"
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#include "video_core/regs_rasterizer.h"
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#include "video_core/regs_texturing.h"
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namespace Pica {
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@ -49,81 +50,7 @@ struct Regs {
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u32 trigger_irq;
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INSERT_PADDING_WORDS(0x2f);
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RasterizerRegs rasterizer;
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struct TextureConfig {
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enum TextureType : u32 {
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Texture2D = 0,
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TextureCube = 1,
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Shadow2D = 2,
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Projection2D = 3,
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ShadowCube = 4,
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Disabled = 5,
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};
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enum WrapMode : u32 {
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ClampToEdge = 0,
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ClampToBorder = 1,
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Repeat = 2,
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MirroredRepeat = 3,
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};
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enum TextureFilter : u32 {
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Nearest = 0,
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Linear = 1,
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};
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union {
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u32 raw;
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BitField<0, 8, u32> r;
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BitField<8, 8, u32> g;
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BitField<16, 8, u32> b;
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BitField<24, 8, u32> a;
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} border_color;
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union {
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BitField<0, 16, u32> height;
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BitField<16, 16, u32> width;
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};
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union {
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BitField<1, 1, TextureFilter> mag_filter;
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BitField<2, 1, TextureFilter> min_filter;
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BitField<8, 2, WrapMode> wrap_t;
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BitField<12, 2, WrapMode> wrap_s;
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BitField<28, 2, TextureType>
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type; ///< @note Only valid for texture 0 according to 3DBrew.
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};
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INSERT_PADDING_WORDS(0x1);
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u32 address;
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u32 GetPhysicalAddress() const {
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return DecodeAddressRegister(address);
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}
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// texture1 and texture2 store the texture format directly after the address
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// whereas texture0 inserts some additional flags inbetween.
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// Hence, we store the format separately so that all other parameters can be described
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// in a single structure.
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};
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enum class TextureFormat : u32 {
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RGBA8 = 0,
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RGB8 = 1,
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RGB5A1 = 2,
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RGB565 = 3,
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RGBA4 = 4,
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IA8 = 5,
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RG8 = 6, ///< @note Also called HILO8 in 3DBrew.
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I8 = 7,
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A8 = 8,
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IA4 = 9,
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I4 = 10,
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A4 = 11,
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ETC1 = 12, // compressed
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ETC1A4 = 13, // compressed
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};
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TexturingRegs texturing;
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enum class LogicOp : u32 {
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Clear = 0,
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@ -144,239 +71,6 @@ struct Regs {
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OrInverted = 15,
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};
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static unsigned NibblesPerPixel(TextureFormat format) {
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switch (format) {
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case TextureFormat::RGBA8:
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return 8;
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case TextureFormat::RGB8:
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return 6;
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case TextureFormat::RGB5A1:
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case TextureFormat::RGB565:
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case TextureFormat::RGBA4:
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case TextureFormat::IA8:
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case TextureFormat::RG8:
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return 4;
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case TextureFormat::I4:
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case TextureFormat::A4:
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return 1;
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case TextureFormat::I8:
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case TextureFormat::A8:
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case TextureFormat::IA4:
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return 2;
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default: // placeholder for yet unknown formats
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UNIMPLEMENTED();
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return 0;
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}
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}
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union {
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BitField<0, 1, u32> texture0_enable;
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BitField<1, 1, u32> texture1_enable;
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BitField<2, 1, u32> texture2_enable;
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};
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TextureConfig texture0;
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INSERT_PADDING_WORDS(0x8);
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BitField<0, 4, TextureFormat> texture0_format;
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BitField<0, 1, u32> fragment_lighting_enable;
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INSERT_PADDING_WORDS(0x1);
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TextureConfig texture1;
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BitField<0, 4, TextureFormat> texture1_format;
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INSERT_PADDING_WORDS(0x2);
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TextureConfig texture2;
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BitField<0, 4, TextureFormat> texture2_format;
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INSERT_PADDING_WORDS(0x21);
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struct FullTextureConfig {
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const bool enabled;
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const TextureConfig config;
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const TextureFormat format;
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};
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const std::array<FullTextureConfig, 3> GetTextures() const {
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return {{
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{texture0_enable.ToBool(), texture0, texture0_format},
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{texture1_enable.ToBool(), texture1, texture1_format},
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{texture2_enable.ToBool(), texture2, texture2_format},
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}};
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}
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// 0xc0-0xff: Texture Combiner (akin to glTexEnv)
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struct TevStageConfig {
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enum class Source : u32 {
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PrimaryColor = 0x0,
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PrimaryFragmentColor = 0x1,
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SecondaryFragmentColor = 0x2,
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Texture0 = 0x3,
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Texture1 = 0x4,
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Texture2 = 0x5,
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Texture3 = 0x6,
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PreviousBuffer = 0xd,
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Constant = 0xe,
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Previous = 0xf,
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};
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enum class ColorModifier : u32 {
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SourceColor = 0x0,
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OneMinusSourceColor = 0x1,
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SourceAlpha = 0x2,
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OneMinusSourceAlpha = 0x3,
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SourceRed = 0x4,
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OneMinusSourceRed = 0x5,
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SourceGreen = 0x8,
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OneMinusSourceGreen = 0x9,
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SourceBlue = 0xc,
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OneMinusSourceBlue = 0xd,
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};
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enum class AlphaModifier : u32 {
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SourceAlpha = 0x0,
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OneMinusSourceAlpha = 0x1,
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SourceRed = 0x2,
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OneMinusSourceRed = 0x3,
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SourceGreen = 0x4,
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OneMinusSourceGreen = 0x5,
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SourceBlue = 0x6,
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OneMinusSourceBlue = 0x7,
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};
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enum class Operation : u32 {
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Replace = 0,
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Modulate = 1,
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Add = 2,
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AddSigned = 3,
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Lerp = 4,
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Subtract = 5,
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Dot3_RGB = 6,
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MultiplyThenAdd = 8,
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AddThenMultiply = 9,
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};
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union {
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u32 sources_raw;
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BitField<0, 4, Source> color_source1;
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BitField<4, 4, Source> color_source2;
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BitField<8, 4, Source> color_source3;
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BitField<16, 4, Source> alpha_source1;
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BitField<20, 4, Source> alpha_source2;
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BitField<24, 4, Source> alpha_source3;
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};
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union {
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u32 modifiers_raw;
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BitField<0, 4, ColorModifier> color_modifier1;
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BitField<4, 4, ColorModifier> color_modifier2;
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BitField<8, 4, ColorModifier> color_modifier3;
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BitField<12, 3, AlphaModifier> alpha_modifier1;
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BitField<16, 3, AlphaModifier> alpha_modifier2;
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BitField<20, 3, AlphaModifier> alpha_modifier3;
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};
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union {
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u32 ops_raw;
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BitField<0, 4, Operation> color_op;
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BitField<16, 4, Operation> alpha_op;
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};
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union {
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u32 const_color;
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BitField<0, 8, u32> const_r;
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BitField<8, 8, u32> const_g;
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BitField<16, 8, u32> const_b;
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BitField<24, 8, u32> const_a;
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};
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union {
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u32 scales_raw;
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BitField<0, 2, u32> color_scale;
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BitField<16, 2, u32> alpha_scale;
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};
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inline unsigned GetColorMultiplier() const {
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return (color_scale < 3) ? (1 << color_scale) : 1;
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}
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inline unsigned GetAlphaMultiplier() const {
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return (alpha_scale < 3) ? (1 << alpha_scale) : 1;
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}
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};
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TevStageConfig tev_stage0;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage1;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage2;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage3;
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INSERT_PADDING_WORDS(0x3);
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enum class FogMode : u32 {
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None = 0,
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Fog = 5,
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Gas = 7,
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};
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union {
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BitField<0, 3, FogMode> fog_mode;
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BitField<16, 1, u32> fog_flip;
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union {
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// Tev stages 0-3 write their output to the combiner buffer if the corresponding bit in
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// these masks are set
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BitField<8, 4, u32> update_mask_rgb;
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BitField<12, 4, u32> update_mask_a;
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bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_rgb & (1 << stage_index));
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}
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bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_a & (1 << stage_index));
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}
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} tev_combiner_buffer_input;
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};
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union {
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u32 raw;
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BitField<0, 8, u32> r;
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BitField<8, 8, u32> g;
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BitField<16, 8, u32> b;
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} fog_color;
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INSERT_PADDING_WORDS(0x4);
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BitField<0, 16, u32> fog_lut_offset;
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INSERT_PADDING_WORDS(0x1);
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u32 fog_lut_data[8];
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TevStageConfig tev_stage4;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage5;
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union {
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u32 raw;
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BitField<0, 8, u32> r;
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BitField<8, 8, u32> g;
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BitField<16, 8, u32> b;
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BitField<24, 8, u32> a;
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} tev_combiner_buffer_color;
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INSERT_PADDING_WORDS(0x2);
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const std::array<Regs::TevStageConfig, 6> GetTevStages() const {
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return {{tev_stage0, tev_stage1, tev_stage2, tev_stage3, tev_stage4, tev_stage5}};
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};
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enum class BlendEquation : u32 {
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Add = 0,
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Subtract = 1,
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@ -1241,26 +935,28 @@ ASSERT_REG_POSITION(rasterizer.scissor_test, 0x65);
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ASSERT_REG_POSITION(rasterizer.viewport_corner, 0x68);
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ASSERT_REG_POSITION(rasterizer.depthmap_enable, 0x6D);
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ASSERT_REG_POSITION(texture0_enable, 0x80);
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ASSERT_REG_POSITION(texture0, 0x81);
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ASSERT_REG_POSITION(texture0_format, 0x8e);
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ASSERT_REG_POSITION(fragment_lighting_enable, 0x8f);
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ASSERT_REG_POSITION(texture1, 0x91);
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ASSERT_REG_POSITION(texture1_format, 0x96);
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ASSERT_REG_POSITION(texture2, 0x99);
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ASSERT_REG_POSITION(texture2_format, 0x9e);
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ASSERT_REG_POSITION(tev_stage0, 0xc0);
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ASSERT_REG_POSITION(tev_stage1, 0xc8);
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ASSERT_REG_POSITION(tev_stage2, 0xd0);
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ASSERT_REG_POSITION(tev_stage3, 0xd8);
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ASSERT_REG_POSITION(tev_combiner_buffer_input, 0xe0);
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ASSERT_REG_POSITION(fog_mode, 0xe0);
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ASSERT_REG_POSITION(fog_color, 0xe1);
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ASSERT_REG_POSITION(fog_lut_offset, 0xe6);
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ASSERT_REG_POSITION(fog_lut_data, 0xe8);
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ASSERT_REG_POSITION(tev_stage4, 0xf0);
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ASSERT_REG_POSITION(tev_stage5, 0xf8);
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ASSERT_REG_POSITION(tev_combiner_buffer_color, 0xfd);
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ASSERT_REG_POSITION(texturing, 0x80);
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ASSERT_REG_POSITION(texturing.texture0_enable, 0x80);
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ASSERT_REG_POSITION(texturing.texture0, 0x81);
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ASSERT_REG_POSITION(texturing.texture0_format, 0x8e);
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ASSERT_REG_POSITION(texturing.fragment_lighting_enable, 0x8f);
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ASSERT_REG_POSITION(texturing.texture1, 0x91);
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ASSERT_REG_POSITION(texturing.texture1_format, 0x96);
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ASSERT_REG_POSITION(texturing.texture2, 0x99);
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ASSERT_REG_POSITION(texturing.texture2_format, 0x9e);
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ASSERT_REG_POSITION(texturing.tev_stage0, 0xc0);
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ASSERT_REG_POSITION(texturing.tev_stage1, 0xc8);
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ASSERT_REG_POSITION(texturing.tev_stage2, 0xd0);
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ASSERT_REG_POSITION(texturing.tev_stage3, 0xd8);
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ASSERT_REG_POSITION(texturing.tev_combiner_buffer_input, 0xe0);
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ASSERT_REG_POSITION(texturing.fog_mode, 0xe0);
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ASSERT_REG_POSITION(texturing.fog_color, 0xe1);
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ASSERT_REG_POSITION(texturing.fog_lut_offset, 0xe6);
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ASSERT_REG_POSITION(texturing.fog_lut_data, 0xe8);
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ASSERT_REG_POSITION(texturing.tev_stage4, 0xf0);
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ASSERT_REG_POSITION(texturing.tev_stage5, 0xf8);
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ASSERT_REG_POSITION(texturing.tev_combiner_buffer_color, 0xfd);
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ASSERT_REG_POSITION(output_merger, 0x100);
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ASSERT_REG_POSITION(framebuffer, 0x110);
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ASSERT_REG_POSITION(lighting, 0x140);
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