Merge pull request #3227 from MerryMage/cro

Allow for partial invalidation of instruction cache
This commit is contained in:
bunnei 2017-12-06 22:43:58 -05:00 committed by GitHub
commit d8ba07a430
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
8 changed files with 26 additions and 5 deletions

View file

@ -4,6 +4,7 @@
#pragma once
#include <cstddef>
#include "common/common_types.h"
#include "core/arm/skyeye_common/arm_regformat.h"
#include "core/arm/skyeye_common/vfp/asm_vfp.h"
@ -33,6 +34,13 @@ public:
/// Clear all instruction cache
virtual void ClearInstructionCache() = 0;
/**
* Invalidate the code cache at a range of addresses.
* @param start_address The starting address of the range to invalidate.
* @param length The length (in bytes) of the range to invalidate.
*/
virtual void InvalidateCacheRange(u32 start_address, size_t length) = 0;
/// Notify CPU emulation that page tables have changed
virtual void PageTableChanged() = 0;

View file

@ -187,6 +187,10 @@ void ARM_Dynarmic::ClearInstructionCache() {
}
}
void ARM_Dynarmic::InvalidateCacheRange(u32 start_address, size_t length) {
jit->InvalidateCacheRange(start_address, length);
}
void ARM_Dynarmic::PageTableChanged() {
current_page_table = Memory::GetCurrentPageTable();

View file

@ -41,6 +41,7 @@ public:
void PrepareReschedule() override;
void ClearInstructionCache() override;
void InvalidateCacheRange(u32 start_address, size_t length) override;
void PageTableChanged() override;
private:

View file

@ -34,6 +34,10 @@ void ARM_DynCom::ClearInstructionCache() {
trans_cache_buf_top = 0;
}
void ARM_DynCom::InvalidateCacheRange(u32, size_t) {
ClearInstructionCache();
}
void ARM_DynCom::PageTableChanged() {
ClearInstructionCache();
}

View file

@ -19,6 +19,7 @@ public:
void Step() override;
void ClearInstructionCache() override;
void InvalidateCacheRange(u32 start_address, size_t length) override;
void PageTableChanged() override;
void SetPC(u32 pc) override;