Cleanup: Logging in Core
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Chin
chinhodado
parent
be8f665142
commit
fa8e6272c8
5 changed files with 274 additions and 600 deletions
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@ -340,7 +340,6 @@ ARMword ARMul_Debug(ARMul_State * state, ARMword pc, ARMword instr)
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mem_Dbugdump();
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}*/
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/*if (pc == 0x0022D168)
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{
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int j = 0;
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@ -1117,7 +1116,6 @@ ARMul_Emulate26 (ARMul_State * state)
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//chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it...
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/* Actual execution of instructions begins here. */
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/* If the condition codes don't match, stop here. */
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if (temp) {
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@ -1178,8 +1176,6 @@ mainswitch:
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tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
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dst = ((data >> msb) << (msb - lsb));
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dst = (dst << lsb) | tmp_rd;
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/*SKYEYE_DBG("BFC instr: msb = %d, lsb = %d, Rd[%d] : 0x%x, dst = 0x%x\n",
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msb, lsb, Rd, state->Reg[Rd], dst);*/
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goto donext;
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} // bfc instr
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else if (((msb >= lsb) && (msb < 32))) {
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@ -1189,8 +1185,6 @@ mainswitch:
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tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
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dst = ((data >> msb) << (msb - lsb)) | tmp_rn;
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dst = (dst << lsb) | tmp_rd;
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/*SKYEYE_DBG("BFI instr:msb = %d, lsb = %d, Rd[%d] : 0x%x, Rn[%d]: 0x%x, dst = 0x%x\n",
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msb, lsb, Rd, state->Reg[Rd], Rn, state->Reg[Rn], dst);*/
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goto donext;
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} // bfi instr
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}
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@ -2215,10 +2209,8 @@ mainswitch:
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state->currentexvald == (u32)ARMul_ReadWord(state, state->currentexaddr + 4))
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enter = true;
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//todo bug this and STREXD and LDREXD http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/CHDGJGGC.html
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if (enter) {
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ARMul_StoreWordN(state, LHS, state->Reg[RHSReg]);
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ARMul_StoreWordN(state,LHS + 4 , state->Reg[RHSReg + 1]);
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@ -2254,9 +2246,6 @@ mainswitch:
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LHPREUPWB ();
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/* Continue with remaining instruction decoding. */
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#endif
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dest = DPSRegRHS;
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WRITESDEST (dest);
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@ -2296,7 +2285,6 @@ mainswitch:
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temp = LHS + GetLS7RHS (state, instr);
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LoadHalfWord (state, instr, temp, LSIGNED);
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break;
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}
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if (BITS (4, 7) == 0xb) {
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/* LDRH immediate offset, no write-back, up, pre indexed. */
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@ -2321,7 +2309,6 @@ mainswitch:
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}
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/* LDR immediate offset, no write-back, up, pre indexed. */
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LHPREUP ();
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}
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#endif
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@ -2342,7 +2329,6 @@ mainswitch:
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if (state->currentexval == (u32)ARMul_LoadHalfWord(state, state->currentexaddr))enter = true;
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//StoreWord(state, lhs, RHS)
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if (state->Aborted) {
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TAKEABORT;
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@ -2396,7 +2382,6 @@ mainswitch:
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WRITESDEST (dest);
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break;
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/* Data Processing Immediate RHS Instructions. */
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case 0x20: /* AND immed */
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@ -2553,8 +2538,6 @@ mainswitch:
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dest = BITS(16, 19);
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dest = ((dest<<12) | BITS(0, 11));
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WRITEDEST(dest);
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//SKYEYE_DBG("In %s, line = %d, pc = 0x%x, instr = 0x%x, R[0:11]: 0x%x, R[16:19]: 0x%x, R[%d]:0x%x\n",
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// __func__, __LINE__, pc, instr, BITS(0, 11), BITS(16, 19), DESTReg, state->Reg[DESTReg]);
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break;
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} else {
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UNDEF_Test;
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@ -2717,7 +2700,6 @@ mainswitch:
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WRITESDEST (~rhs);
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break;
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/* Single Data Transfer Immediate RHS Instructions. */
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case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */
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@ -2849,7 +2831,6 @@ mainswitch:
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state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
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break;
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case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */
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(void) StoreWord (state, instr, LHS - LSImmRHS);
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break;
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@ -2946,7 +2927,6 @@ mainswitch:
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LSBase = temp;
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break;
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/* Single Data Transfer Register RHS Instructions. */
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case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */
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@ -3234,11 +3214,9 @@ mainswitch:
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int Rm = 0;
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/* utxb */
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if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) {
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Rm = (RHS >> (8 * BITS(10, 11))) & 0xff;
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DEST = Rm;
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}
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}
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#endif
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if (BIT (4)) {
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@ -3285,7 +3263,6 @@ mainswitch:
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state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
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break;
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case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */
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if (BIT (4)) {
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#ifdef MODE32
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@ -3489,7 +3466,6 @@ mainswitch:
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LSBase = temp;
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break;
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/* Multiple Data Transfer Instructions. */
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case 0x80: /* Store, No WriteBack, Post Dec. */
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@ -3636,7 +3612,6 @@ mainswitch:
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LOADSMULT (instr, temp + 4L, temp + LSMNumRegs);
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break;
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/* Branch forward. */
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case 0xa0:
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case 0xa1:
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@ -3650,7 +3625,6 @@ mainswitch:
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FLUSHPIPE;
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break;
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/* Branch backward. */
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case 0xa8:
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case 0xa9:
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@ -3664,7 +3638,6 @@ mainswitch:
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FLUSHPIPE;
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break;
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/* Branch and Link forward. */
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case 0xb0:
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case 0xb1:
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@ -3690,10 +3663,8 @@ mainswitch:
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printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
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#endif
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break;
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/* Branch and Link backward. */
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case 0xb8:
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case 0xb9:
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@ -3712,18 +3683,14 @@ mainswitch:
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state->Reg[15] = pc + 8 + NEGBRANCH;
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FLUSHPIPE;
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#ifdef callstacker
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memset(a, 0, 256);
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aufloeser(a, state->Reg[15]);
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printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
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#endif
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break;
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/* Co-Processor Data Transfers. */
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case 0xc4:
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if ((instr & 0x0FF00FF0) == 0xC400B10) { //vmov BIT(0-3), BIT(12-15), BIT(16-20), vmov d0, r0, r0
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@ -3859,7 +3826,6 @@ mainswitch:
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ARMul_LDC (state, instr, lhs);
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break;
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/* Co-Processor Register Transfers (MCR) and Data Ops. */
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case 0xe2:
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@ -3891,7 +3857,6 @@ mainswitch:
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ARMul_CDP (state, instr);
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break;
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/* Co-Processor Register Transfers (MRC) and Data Ops. */
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case 0xe1:
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case 0xe3:
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@ -3916,7 +3881,6 @@ mainswitch:
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ARMul_CDP (state, instr);
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break;
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/* SWI instruction. */
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case 0xf0:
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case 0xf1:
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@ -3936,7 +3900,7 @@ mainswitch:
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case 0xff:
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//svc_Execute(state, BITS(0, 23));
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HLE::CallSVC(instr);
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break;
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}
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}
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@ -4118,7 +4082,6 @@ TEST_EMULATE:
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// continue;
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else if (state->Emulate != RUN)
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break;
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}
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while (state->NumInstrsToExecute);
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@ -4156,7 +4119,6 @@ exit:
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static FILE *fd;
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/*if (!init) {
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fd = fopen("./pc.txt", "w");
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if (!fd) {
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exit(-1);
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@ -4725,8 +4687,6 @@ out:
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address, DEST); \
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}
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static unsigned
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LoadWord (ARMul_State * state, ARMword instr, ARMword address) {
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ARMword dest;
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@ -5158,7 +5118,6 @@ out:
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/*chy 2004-05-23 chy goto end */
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if (state->Aborted)
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goto L_ldm_makeabort;
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}
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if (BIT (15) && !state->Aborted)
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@ -5202,7 +5161,6 @@ L_ldm_makeabort:
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LSBase = WBBase;
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}
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/* chy 2005-11-24, over */
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}
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/* This function does the work of loading the registers listed in an LDM
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@ -5405,7 +5363,6 @@ L_ldm_s_makeabort:
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//chy 2004-05-23, needn't store other when aborted
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if (state->Aborted)
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goto L_stm_takeabort;
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}
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//chy 2004-05-23,should compare the Abort Models
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@ -5508,7 +5465,6 @@ L_stm_takeabort:
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/* Restore the correct bank. */
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(void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
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//chy 2004-05-23,should compare the Abort Models
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L_stm_s_takeabort:
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if (BIT (21) && LHSReg != 15) {
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@ -5763,7 +5719,6 @@ L_stm_s_takeabort:
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TAKEABORT;
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}
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if (enter) {
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ARMul_StoreByte(state, lhs, RHS);
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state->Reg[DESTReg] = 0;
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@ -6285,7 +6240,7 @@ L_stm_s_takeabort:
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u32 rm = ((state->Reg[BITS(0, 3)] >> rotation) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotation)) & 0xFF) & 0xFF);
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if (rm & 0x80)
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rm |= 0xffffff00;
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// SXTB, otherwise SXTAB
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if (BITS(16, 19) == 0xf)
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state->Reg[BITS(12, 15)] = rm;
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@ -6371,7 +6326,7 @@ L_stm_s_takeabort:
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const s16 max = 0xFFFF >> (16 - num_bits);
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s16 rn_lo = (state->Reg[rn_idx]);
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s16 rn_hi = (state->Reg[rn_idx] >> 16);
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if (max < rn_lo) {
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rn_lo = max;
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SETQ;
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@ -6379,7 +6334,7 @@ L_stm_s_takeabort:
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rn_lo = 0;
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SETQ;
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}
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if (max < rn_hi) {
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rn_hi = max;
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SETQ;
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@ -6387,14 +6342,14 @@ L_stm_s_takeabort:
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rn_hi = 0;
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SETQ;
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}
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state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF);
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return 1;
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}
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else if (op2 == 0x03) {
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const u8 rotate = BITS(10, 11) * 8;
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const u32 rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFF) & 0xFF);
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if (BITS(16, 19) == 0xf)
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/* UXTB */
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state->Reg[BITS(12, 15)] = rm;
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