Mirrors/pebble
1
0
Fork 0
mirror of https://github.com/google/pebble.git synced 2025-05-31 07:23:12 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Import of the watch repository from Pebble

Browse source
This commit is contained in:
Matthieu Jeanson 2024-12-12 16:43:03 -08:00 • committed by Katharine Berry
commit 3b92768480
10334 changed files with 2564465 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

109
src/fw/startup/irq_stm32f7.def Normal file
View file

@ -0,0 +1,109 @@
IRQ_DEF(WWDG_IRQHandler) // Window WatchDog
IRQ_DEF(PVD_IRQHandler) // PVD through EXTI Line detection
IRQ_DEF(TAMP_STAMP_IRQHandler) // Tamper and TimeStamps through the EXTI line
IRQ_DEF(RTC_WKUP_IRQHandler) // RTC Wakeup through the EXTI line
IRQ_DEF(FLASH_IRQHandler) // FLASH
IRQ_DEF(RCC_IRQHandler) // RCC
IRQ_DEF(EXTI0_IRQHandler) // EXTI Line0
IRQ_DEF(EXTI1_IRQHandler) // EXTI Line1
IRQ_DEF(EXTI2_IRQHandler) // EXTI Line2
IRQ_DEF(EXTI3_IRQHandler) // EXTI Line3
IRQ_DEF(EXTI4_IRQHandler) // EXTI Line4
IRQ_DEF(DMA1_Stream0_IRQHandler) // DMA1 Stream 0
IRQ_DEF(DMA1_Stream1_IRQHandler) // DMA1 Stream 1
IRQ_DEF(DMA1_Stream2_IRQHandler) // DMA1 Stream 2
IRQ_DEF(DMA1_Stream3_IRQHandler) // DMA1 Stream 3
IRQ_DEF(DMA1_Stream4_IRQHandler) // DMA1 Stream 4
IRQ_DEF(DMA1_Stream5_IRQHandler) // DMA1 Stream 5
IRQ_DEF(DMA1_Stream6_IRQHandler) // DMA1 Stream 6
IRQ_DEF(ADC_IRQHandler) // ADC1, ADC2 and ADC3s
IRQ_DEF(CAN1_TX_IRQHandler) // CAN1 TX
IRQ_DEF(CAN1_RX0_IRQHandler) // CAN1 RX0
IRQ_DEF(CAN1_RX1_IRQHandler) // CAN1 RX1
IRQ_DEF(CAN1_SCE_IRQHandler) // CAN1 SCE
IRQ_DEF(EXTI9_5_IRQHandler) // External Line[9:5]s
IRQ_DEF(TIM1_BRK_TIM9_IRQHandler) // TIM1 Break and TIM9
IRQ_DEF(TIM1_UP_TIM10_IRQHandler) // TIM1 Update and TIM10
IRQ_DEF(TIM1_TRG_COM_TIM11_IRQHandler) // TIM1 Trigger and Commutation and TIM11
IRQ_DEF(TIM1_CC_IRQHandler) // TIM1 Capture Compare
IRQ_DEF(TIM2_IRQHandler) // TIM2
IRQ_DEF(TIM3_IRQHandler) // TIM3
IRQ_DEF(TIM4_IRQHandler) // TIM4
IRQ_DEF(I2C1_EV_IRQHandler) // I2C1 Event
IRQ_DEF(I2C1_ER_IRQHandler) // I2C1 Error
IRQ_DEF(I2C2_EV_IRQHandler) // I2C2 Event
IRQ_DEF(I2C2_ER_IRQHandler) // I2C2 Error
IRQ_DEF(SPI1_IRQHandler) // SPI1
IRQ_DEF(SPI2_IRQHandler) // SPI2
IRQ_DEF(USART1_IRQHandler) // USART1
IRQ_DEF(USART2_IRQHandler) // USART2
IRQ_DEF(USART3_IRQHandler) // USART3
IRQ_DEF(EXTI15_10_IRQHandler) // External Line[15:10]s
IRQ_DEF(RTC_Alarm_IRQHandler) // RTC Alarm (A and B) through EXTI Line
IRQ_DEF(OTG_FS_WKUP_IRQHandler) // USB OTG FS Wakeup through EXTI line
IRQ_DEF(TIM8_BRK_TIM12_IRQHandler) // TIM8 Break and TIM12
IRQ_DEF(TIM8_UP_TIM13_IRQHandler) // TIM8 Update and TIM13
IRQ_DEF(TIM8_TRG_COM_TIM14_IRQHandler) // TIM8 Trigger and Commutation and TIM14
IRQ_DEF(TIM8_CC_IRQHandler) // TIM8 Capture Compare
IRQ_DEF(DMA1_Stream7_IRQHandler) // DMA1 Stream7
IRQ_DEF(FMC_IRQHandler) // FMC
IRQ_DEF(SDMMC1_IRQHandler) // SDMMC1
IRQ_DEF(TIM5_IRQHandler) // TIM5
IRQ_DEF(SPI3_IRQHandler) // SPI3
IRQ_DEF(UART4_IRQHandler) // UART4
IRQ_DEF(UART5_IRQHandler) // UART5
IRQ_DEF(TIM6_DAC_IRQHandler) // TIM6 and DAC1&2 underrun errors
IRQ_DEF(TIM7_IRQHandler) // TIM7
IRQ_DEF(DMA2_Stream0_IRQHandler) // DMA2 Stream 0
IRQ_DEF(DMA2_Stream1_IRQHandler) // DMA2 Stream 1
IRQ_DEF(DMA2_Stream2_IRQHandler) // DMA2 Stream 2
IRQ_DEF(DMA2_Stream3_IRQHandler) // DMA2 Stream 3
IRQ_DEF(DMA2_Stream4_IRQHandler) // DMA2 Stream 4
IRQ_DEF(ETH_IRQHandler) // Ethernet
IRQ_DEF(ETH_WKUP_IRQHandler) // Ethernet Wakeup through EXTI line
IRQ_DEF(CAN2_TX_IRQHandler) // CAN2 TX
IRQ_DEF(CAN2_RX0_IRQHandler) // CAN2 RX0
IRQ_DEF(CAN2_RX1_IRQHandler) // CAN2 RX1
IRQ_DEF(CAN2_SCE_IRQHandler) // CAN2 SCE
IRQ_DEF(OTG_FS_IRQHandler) // USB OTG FS
IRQ_DEF(DMA2_Stream5_IRQHandler) // DMA2 Stream 5
IRQ_DEF(DMA2_Stream6_IRQHandler) // DMA2 Stream 6
IRQ_DEF(DMA2_Stream7_IRQHandler) // DMA2 Stream 7
IRQ_DEF(USART6_IRQHandler) // USART6
IRQ_DEF(I2C3_EV_IRQHandler) // I2C3 event
IRQ_DEF(I2C3_ER_IRQHandler) // I2C3 error
IRQ_DEF(OTG_HS_EP1_OUT_IRQHandler) // USB OTG HS End Point 1 Out
IRQ_DEF(OTG_HS_EP1_IN_IRQHandler) // USB OTG HS End Point 1 In
IRQ_DEF(OTG_HS_WKUP_IRQHandler) // USB OTG HS Wakeup through EXTI
IRQ_DEF(OTG_HS_IRQHandler) // USB OTG HS
IRQ_DEF(DCMI_IRQHandler) // DCMI
IRQ_DEF(CRYP_IRQHandler) // CRYP crypto
IRQ_DEF(HASH_RNG_IRQHandler) // Hash and Rng
IRQ_DEF(FPU_IRQHandler) // FPU
IRQ_DEF(UART7_IRQHandler) // UART7
IRQ_DEF(UART8_IRQHandler) // UART8
IRQ_DEF(SPI4_IRQHandler) // SPI4
IRQ_DEF(SPI5_IRQHandler) // SPI5
IRQ_DEF(SPI6_IRQHandler) // SPI6
IRQ_DEF(SAI1_IRQHandler) // SAI1
IRQ_DEF(LTDC_IRQHandler) // LTDC_IRQHandler
IRQ_DEF(LTDC_ER_IRQHandler) // LTDC_ER_IRQHandler
IRQ_DEF(DMA2D_IRQHandler) // DMA2D
IRQ_DEF(SAI2_IRQHandler) // SAI2
IRQ_DEF(QUADSPI_IRQHandler) // Quad SPI
IRQ_DEF(LPTIM1_IRQHandler) // LP TIM1
IRQ_DEF(CEC_IRQHandler) // HDMI-CEC
IRQ_DEF(I2C4_EV_IRQHandler) // I2C4 Event
IRQ_DEF(I2C4_ER_IRQHandler) // I2C4 Error
IRQ_DEF(SPDIF_RX_IRQHandler) // SPDIF-RX
IRQ_DEF(DFSDM0_IRQHandler) // DFSDM Filter1
IRQ_DEF(DFSDM1_IRQHandler) // DFSDM Filter2
IRQ_DEF(DFSDM2_IRQHandler) // DFSDM Filter3
IRQ_DEF(DFSDM3_IRQHandler) // DFSDM Filter4
IRQ_DEF(SDMMC2_IRQHandler) // SDMMC2
IRQ_DEF(CAN3_TX_IRQHandler) // CAN3 TX
IRQ_DEF(CAN3_RX0_IRQHandler) // CAN3 RX0
IRQ_DEF(CAN3_RX1_IRQHandler) // CAN3 RX1
IRQ_DEF(CAN3_SCE_IRQHandler) // CAN3 SCE
IRQ_DEF(JPEG_IRQHandler) // JPEG
IRQ_DEF(MDIOS_IRQHandler) // MDIO Slave