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Import of the watch repository from Pebble
This commit is contained in:
Matthieu Jeanson
Katharine Berry
commit
3b92768480
10334 changed files with 2564465 additions and 0 deletions
320
third_party/ARM/string/memcpy-armv7m.S
vendored
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320
third_party/ARM/string/memcpy-armv7m.S
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@ -0,0 +1,320 @@
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/*
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* Copyright (c) 2013 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* This memcpy routine is optimised for Cortex-M3/M4 cores with/without
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unaligned access.
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If compiled with GCC, this file should be enclosed within following
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pre-processing check:
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if defined (__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
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Prototype: void *memcpy (void *dst, const void *src, size_t count);
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The job will be done in 5 steps.
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Step 1: Align src/dest pointers, copy mis-aligned if fail to align both
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Step 2: Repeatedly copy big block size of __OPT_BIG_BLOCK_SIZE
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Step 3: Repeatedly copy big block size of __OPT_MID_BLOCK_SIZE
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Step 4: Copy word by word
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Step 5: Copy byte-to-byte
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Tunable options:
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__OPT_BIG_BLOCK_SIZE: Size of big block in words. Default to 64.
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__OPT_MID_BLOCK_SIZE: Size of big block in words. Default to 16.
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*/
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#if __ARM_ARCH_ISA_THUMB >= 2
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#ifndef __OPT_BIG_BLOCK_SIZE
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#define __OPT_BIG_BLOCK_SIZE (4 * 16)
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#endif
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#ifndef __OPT_MID_BLOCK_SIZE
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#define __OPT_MID_BLOCK_SIZE (4 * 4)
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#endif
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#if __OPT_BIG_BLOCK_SIZE == 16
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#define BEGIN_UNROLL_BIG_BLOCK \
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.irp offset, 0,4,8,12
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#elif __OPT_BIG_BLOCK_SIZE == 32
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#define BEGIN_UNROLL_BIG_BLOCK \
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.irp offset, 0,4,8,12,16,20,24,28
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#elif __OPT_BIG_BLOCK_SIZE == 64
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#define BEGIN_UNROLL_BIG_BLOCK \
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.irp offset, 0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60
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#else
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#error "Illegal __OPT_BIG_BLOCK_SIZE"
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#endif
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#if __OPT_MID_BLOCK_SIZE == 8
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#define BEGIN_UNROLL_MID_BLOCK \
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.irp offset, 0,4
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#elif __OPT_MID_BLOCK_SIZE == 16
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#define BEGIN_UNROLL_MID_BLOCK \
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.irp offset, 0,4,8,12
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#else
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#error "Illegal __OPT_MID_BLOCK_SIZE"
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#endif
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#define END_UNROLL .endr
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.syntax unified
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.text
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.align 2
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.global memcpy
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.thumb
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.thumb_func
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.type memcpy, %function
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memcpy:
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@ r0: dst
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@ r1: src
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@ r2: len
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#ifdef __ARM_FEATURE_UNALIGNED
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/* In case of UNALIGNED access supported, ip is not used in
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function body. */
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mov ip, r0
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#else
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push {r0}
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#endif
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orr r3, r1, r0
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ands r3, r3, #3
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bne .Lmisaligned_copy
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.Lbig_block:
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subs r2, __OPT_BIG_BLOCK_SIZE
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blo .Lmid_block
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/* Kernel loop for big block copy */
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.align 2
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.Lbig_block_loop:
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BEGIN_UNROLL_BIG_BLOCK
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#ifdef __ARM_ARCH_7EM__
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ldr r3, [r1], #4
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str r3, [r0], #4
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END_UNROLL
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#else /* __ARM_ARCH_7M__ */
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ldr r3, [r1, \offset]
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str r3, [r0, \offset]
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END_UNROLL
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adds r0, __OPT_BIG_BLOCK_SIZE
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adds r1, __OPT_BIG_BLOCK_SIZE
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#endif
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subs r2, __OPT_BIG_BLOCK_SIZE
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bhs .Lbig_block_loop
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.Lmid_block:
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adds r2, __OPT_BIG_BLOCK_SIZE - __OPT_MID_BLOCK_SIZE
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blo .Lcopy_word_by_word
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/* Kernel loop for mid-block copy */
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.align 2
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.Lmid_block_loop:
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BEGIN_UNROLL_MID_BLOCK
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#ifdef __ARM_ARCH_7EM__
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ldr r3, [r1], #4
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str r3, [r0], #4
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END_UNROLL
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#else /* __ARM_ARCH_7M__ */
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ldr r3, [r1, \offset]
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str r3, [r0, \offset]
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END_UNROLL
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adds r0, __OPT_MID_BLOCK_SIZE
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adds r1, __OPT_MID_BLOCK_SIZE
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#endif
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subs r2, __OPT_MID_BLOCK_SIZE
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bhs .Lmid_block_loop
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.Lcopy_word_by_word:
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adds r2, __OPT_MID_BLOCK_SIZE - 4
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blo .Lcopy_less_than_4
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/* Kernel loop for small block copy */
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.align 2
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.Lcopy_word_by_word_loop:
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ldr r3, [r1], #4
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str r3, [r0], #4
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subs r2, #4
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bhs .Lcopy_word_by_word_loop
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.Lcopy_less_than_4:
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adds r2, #4
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beq .Ldone
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lsls r2, r2, #31
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itt ne
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ldrbne r3, [r1], #1
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strbne r3, [r0], #1
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bcc .Ldone
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#ifdef __ARM_FEATURE_UNALIGNED
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ldrh r3, [r1]
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strh r3, [r0]
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#else
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ldrb r3, [r1]
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strb r3, [r0]
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ldrb r3, [r1, #1]
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strb r3, [r0, #1]
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#endif /* __ARM_FEATURE_UNALIGNED */
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.Ldone:
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#ifdef __ARM_FEATURE_UNALIGNED
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mov r0, ip
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#else
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pop {r0}
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#endif
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bx lr
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.align 2
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.Lmisaligned_copy:
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#ifdef __ARM_FEATURE_UNALIGNED
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/* Define label DST_ALIGNED to BIG_BLOCK. It will go to aligned copy
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once destination is adjusted to aligned. */
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#define Ldst_aligned Lbig_block
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/* Copy word by word using LDR when alignment can be done in hardware,
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i.e., SCTLR.A is set, supporting unaligned access in LDR and STR. */
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cmp r2, #8
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blo .Lbyte_copy
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/* if src is aligned, just go to the big block loop. */
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lsls r3, r1, #30
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beq .Ldst_aligned
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#else
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/* if len < 12, misalignment adjustment has more overhead than
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just byte-to-byte copy. Also, len must >=8 to guarantee code
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afterward work correctly. */
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cmp r2, #12
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blo .Lbyte_copy
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#endif /* __ARM_FEATURE_UNALIGNED */
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/* Align dst only, not trying to align src. That is the because
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handling of aligned src and misaligned dst need more overhead than
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otherwise. By doing this the worst case is when initial src is aligned,
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additional up to 4 byte additional copy will executed, which is
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acceptable. */
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ands r3, r0, #3
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beq .Ldst_aligned
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rsb r3, #4
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subs r2, r3
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lsls r3, r3, #31
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itt ne
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ldrbne r3, [r1], #1
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strbne r3, [r0], #1
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bcc .Ldst_aligned
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#ifdef __ARM_FEATURE_UNALIGNED
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ldrh r3, [r1], #2
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strh r3, [r0], #2
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b .Ldst_aligned
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#else
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ldrb r3, [r1], #1
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strb r3, [r0], #1
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ldrb r3, [r1], #1
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strb r3, [r0], #1
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/* Now that dst is aligned */
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.Ldst_aligned:
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/* if r1 is aligned now, it means r0/r1 has the same misalignment,
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and they are both aligned now. Go aligned copy. */
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ands r3, r1, #3
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beq .Lbig_block
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/* dst is aligned, but src isn't. Misaligned copy. */
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push {r4, r5}
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subs r2, #4
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/* Backward r1 by misaligned bytes, to make r1 aligned.
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Since we need to restore r1 to unaligned address after the loop,
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we need keep the offset bytes to ip and sub it from r1 afterward. */
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subs r1, r3
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rsb ip, r3, #4
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/* Pre-load on word */
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ldr r4, [r1], #4
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cmp r3, #2
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beq .Lmisaligned_copy_2_2
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cmp r3, #3
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beq .Lmisaligned_copy_3_1
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.macro mis_src_copy shift
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1:
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lsrs r4, r4, \shift
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ldr r3, [r1], #4
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lsls r5, r3, 32-\shift
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orr r4, r4, r5
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str r4, [r0], #4
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mov r4, r3
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subs r2, #4
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bhs 1b
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.endm
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.Lmisaligned_copy_1_3:
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mis_src_copy shift=8
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b .Lsrc_misaligned_tail
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.Lmisaligned_copy_3_1:
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mis_src_copy shift=24
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b .Lsrc_misaligned_tail
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.Lmisaligned_copy_2_2:
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/* For 2_2 misalignment, ldr is still faster than 2 x ldrh. */
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mis_src_copy shift=16
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.Lsrc_misaligned_tail:
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adds r2, #4
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subs r1, ip
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pop {r4, r5}
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#endif /* __ARM_FEATURE_UNALIGNED */
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.Lbyte_copy:
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subs r2, #4
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blo .Lcopy_less_than_4
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.Lbyte_copy_loop:
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subs r2, #1
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ldrb r3, [r1], #1
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strb r3, [r0], #1
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bhs .Lbyte_copy_loop
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ldrb r3, [r1]
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strb r3, [r0]
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ldrb r3, [r1, #1]
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strb r3, [r0, #1]
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ldrb r3, [r1, #2]
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strb r3, [r0, #2]
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#ifdef __ARM_FEATURE_UNALIGNED
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mov r0, ip
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#else
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pop {r0}
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#endif
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bx lr
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.size memcpy, .-memcpy
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#endif
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117
third_party/ARM/string/memset-thumb2.S
vendored
Normal file
117
third_party/ARM/string/memset-thumb2.S
vendored
Normal file
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@ -0,0 +1,117 @@
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/*
|
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* Copyright (c) 2015 ARM Ltd
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the company may not be used to endorse or promote
|
||||
* products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
|
||||
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* modified 2016-06-22:
|
||||
* converted aeabi_memset to normal memset (save r0, different argument order) */
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||||
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||||
#if __ARM_ARCH_ISA_THUMB >= 2
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||||
.syntax unified
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||||
.text
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||||
.align 2
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||||
.thumb
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||||
.thumb_func
|
||||
.global memset
|
||||
.type memset, %function
|
||||
memset:
|
||||
.cfi_startproc
|
||||
push {r0, r4, r5, r6}
|
||||
lsls r4, r0, #30
|
||||
beq .L14
|
||||
subs r4, r2, #1
|
||||
cmp r2, #0
|
||||
beq .L16
|
||||
uxtb r5, r1
|
||||
mov r3, r0
|
||||
b .L4
|
||||
.L6:
|
||||
subs r2, r4, #1
|
||||
cbz r4, .L16
|
||||
mov r4, r2
|
||||
.L4:
|
||||
strb r5, [r3], #1
|
||||
lsls r2, r3, #30
|
||||
bne .L6
|
||||
.L2:
|
||||
cmp r4, #3
|
||||
bls .L11
|
||||
uxtb r5, r1
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||||
orr r5, r5, r5, lsl #8
|
||||
cmp r4, #15
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||||
orr r5, r5, r5, lsl #16
|
||||
bls .L9
|
||||
add r2, r3, #16
|
||||
mov r6, r4
|
||||
.L10:
|
||||
subs r6, r6, #16
|
||||
cmp r6, #15
|
||||
str r5, [r2, #-16]
|
||||
str r5, [r2, #-12]
|
||||
str r5, [r2, #-8]
|
||||
str r5, [r2, #-4]
|
||||
add r2, r2, #16
|
||||
bhi .L10
|
||||
sub r2, r4, #16
|
||||
bic r2, r2, #15
|
||||
and r4, r4, #15
|
||||
adds r2, r2, #16
|
||||
cmp r4, #3
|
||||
add r3, r3, r2
|
||||
bls .L11
|
||||
.L9:
|
||||
mov r6, r3
|
||||
mov r2, r4
|
||||
.L12:
|
||||
subs r2, r2, #4
|
||||
cmp r2, #3
|
||||
str r5, [r6], #4
|
||||
bhi .L12
|
||||
subs r2, r4, #4
|
||||
bic r2, r2, #3
|
||||
adds r2, r2, #4
|
||||
add r3, r3, r2
|
||||
and r4, r4, #3
|
||||
.L11:
|
||||
cbz r4, .L16
|
||||
uxtb r1, r1
|
||||
add r4, r4, r3
|
||||
.L13:
|
||||
strb r1, [r3], #1
|
||||
cmp r3, r4
|
||||
bne .L13
|
||||
.L16:
|
||||
pop {r0, r4, r5, r6}
|
||||
bx lr
|
||||
.L14:
|
||||
mov r4, r2
|
||||
mov r3, r0
|
||||
b .L2
|
||||
.cfi_endproc
|
||||
.size memset, . - memset
|
||||
|
||||
#endif
|
||||
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