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88 lines
3.6 KiB
C
88 lines
3.6 KiB
C
/*
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* Copyright 2024 Google LLC
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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// Instruction cache and data cache are entirely separate. Therefore, you must both flush data
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// cache _and_ invalidate instruction cache for that region in order to properly execute new code.
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// A cache flush means the data is written out from the cache into memory. A cache invalidate
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// means the data in the cache is thrown out and will be reloaded from memory on the next access.
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// A flush does keep the data still in cache, so if you want to write out and invalidate, you want
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// to use flush_invalidate.
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// All cache operations MUST operate on the cache line size. You can safely flush memory that isn't
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// part of your buffer, but invalidation CAN AND WILL destroy other memory! Be very careful!
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// The cache line size on Cortex-M7 is 32 bytes.
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//! Enable instruction cache.
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void icache_enable(void);
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//! Disable instruction cache.
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void icache_disable(void);
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//! Returns whether or not ICache is enabled
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bool icache_is_enabled(void);
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//! Returns line size of ICache.
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uint32_t icache_line_size(void);
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//! Invalidate entire instruction cache.
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void icache_invalidate_all(void);
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//! Invalidate instruction cache for `addr` for `size` bytes.
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//! `addr` and `size` should both be aligned by the cache line size.
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void icache_invalidate(void *addr, size_t size);
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//! Enable data cache.
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void dcache_enable(void);
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//! Disable data cache.
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void dcache_disable(void);
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//! Returns whether or not DCache is enabled
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bool dcache_is_enabled(void);
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//! Returns line size of DCache.
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uint32_t dcache_line_size(void);
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//! Flush entire data cache.
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void dcache_flush_all(void);
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//! Invalidate entire data cache.
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void dcache_invalidate_all(void);
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//! Flush, then invalidate entire data cache.
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void dcache_flush_invalidate_all(void);
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//! Flush data cache for `addr` for `size` bytes.
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//! `addr` and `size` should both be aligned by the cache line size.
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void dcache_flush(const void *addr, size_t size);
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//! Invalidate data cache for `addr` for `size` bytes.
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//! `addr` and `size` should both be aligned by the cache line size.
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void dcache_invalidate(void *addr, size_t size);
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//! Flush, then invalidate data cache for `addr` for `size` bytes.
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//! `addr` and `size` should both be aligned by the cache line size.
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void dcache_flush_invalidate(const void *addr, size_t size);
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//! Aligns an address and size so that they are both aligned to the ICache line size, and still
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//! covers the range requested.
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void icache_align(uintptr_t *addr, size_t *size);
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//! Aligns an address and size so that they are both aligned to the DCache line size, and still
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//! covers the range requested.
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void dcache_align(uintptr_t *addr, size_t *size);
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//! For aligning things to work with the data cache, you will want to check what the cache line
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//! size is, and align accordingly. However, the hardware peripheral also might require a minimum
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//! alignment. So you pass the minimum alignment in bytes into `min`, and the return value is the
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//! mask you can apply to get the minimum aligned address.
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uint32_t dcache_alignment_mask_minimum(uint32_t min);
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