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This commit is contained in:
IndecisiveTurtle 2025-07-10 12:09:04 +03:00
parent 27b243cae6
commit 024f41f282
5 changed files with 68 additions and 8 deletions
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2
src/shader_recompiler/frontend/translate/data_share.cpp
View file

@ -277,7 +277,7 @@ void Translator::DS_SWIZZLE_B32(const GcnInst& inst) {
const u8 offset0 = inst.control.ds.offset0; const u8 offset0 = inst.control.ds.offset0;
const u8 offset1 = inst.control.ds.offset1; const u8 offset1 = inst.control.ds.offset1;
const IR::U32 src{GetSrc(inst.src[0])}; const IR::U32 src{GetSrc(inst.src[0])};
ASSERT(offset1 & 0x80); // ASSERT(offset1 & 0x80);
const IR::U32 lane_id = ir.LaneId(); const IR::U32 lane_id = ir.LaneId();
const IR::U32 id_in_group = ir.BitwiseAnd(lane_id, ir.Imm32(0b11)); const IR::U32 id_in_group = ir.BitwiseAnd(lane_id, ir.Imm32(0b11));
const IR::U32 base = ir.ShiftLeftLogical(id_in_group, ir.Imm32(1)); const IR::U32 base = ir.ShiftLeftLogical(id_in_group, ir.Imm32(1));

12
src/shader_recompiler/ir/microinstruction.cpp
View file

@ -92,7 +92,6 @@ bool Inst::MayHaveSideEffects() const noexcept {
case Opcode::WriteSharedU32: case Opcode::WriteSharedU32:
case Opcode::WriteSharedU64: case Opcode::WriteSharedU64:
case Opcode::SharedAtomicIAdd32: case Opcode::SharedAtomicIAdd32:
case Opcode::SharedAtomicIAdd64:
case Opcode::SharedAtomicISub32: case Opcode::SharedAtomicISub32:
case Opcode::SharedAtomicSMin32: case Opcode::SharedAtomicSMin32:
case Opcode::SharedAtomicUMin32: case Opcode::SharedAtomicUMin32:
@ -103,6 +102,17 @@ bool Inst::MayHaveSideEffects() const noexcept {
case Opcode::SharedAtomicAnd32: case Opcode::SharedAtomicAnd32:
case Opcode::SharedAtomicOr32: case Opcode::SharedAtomicOr32:
case Opcode::SharedAtomicXor32: case Opcode::SharedAtomicXor32:
case Opcode::SharedAtomicIAdd64:
case Opcode::SharedAtomicISub64:
case Opcode::SharedAtomicSMin64:
case Opcode::SharedAtomicUMin64:
case Opcode::SharedAtomicSMax64:
case Opcode::SharedAtomicUMax64:
case Opcode::SharedAtomicInc64:
case Opcode::SharedAtomicDec64:
case Opcode::SharedAtomicAnd64:
case Opcode::SharedAtomicOr64:
case Opcode::SharedAtomicXor64:
case Opcode::ImageWrite: case Opcode::ImageWrite:
case Opcode::ImageAtomicIAdd32: case Opcode::ImageAtomicIAdd32:
case Opcode::ImageAtomicSMin32: case Opcode::ImageAtomicSMin32:

10
src/shader_recompiler/ir/passes/shader_info_collection_pass.cpp
View file

@ -55,6 +55,16 @@ void Visit(Info& info, const IR::Inst& inst) {
info.shared_types |= IR::Type::U32; info.shared_types |= IR::Type::U32;
break; break;
case IR::Opcode::SharedAtomicIAdd64: case IR::Opcode::SharedAtomicIAdd64:
case IR::Opcode::SharedAtomicISub64:
case IR::Opcode::SharedAtomicSMin64:
case IR::Opcode::SharedAtomicUMin64:
case IR::Opcode::SharedAtomicSMax64:
case IR::Opcode::SharedAtomicUMax64:
case IR::Opcode::SharedAtomicInc64:
case IR::Opcode::SharedAtomicDec64:
case IR::Opcode::SharedAtomicAnd64:
case IR::Opcode::SharedAtomicOr64:
case IR::Opcode::SharedAtomicXor64:
info.uses_shared_int64_atomics = true; info.uses_shared_int64_atomics = true;
[[fallthrough]]; [[fallthrough]];
case IR::Opcode::LoadSharedU64: case IR::Opcode::LoadSharedU64:

10
src/shader_recompiler/ir/passes/shared_memory_simplify_pass.cpp
View file

@ -15,6 +15,16 @@ static bool Requires16BitSharedAtomic(const IR::Inst& inst) {
static bool Requires64BitSharedAtomic(const IR::Inst& inst) { static bool Requires64BitSharedAtomic(const IR::Inst& inst) {
switch (inst.GetOpcode()) { switch (inst.GetOpcode()) {
case IR::Opcode::SharedAtomicIAdd64: case IR::Opcode::SharedAtomicIAdd64:
case IR::Opcode::SharedAtomicISub64:
case IR::Opcode::SharedAtomicSMin64:
case IR::Opcode::SharedAtomicUMin64:
case IR::Opcode::SharedAtomicSMax64:
case IR::Opcode::SharedAtomicUMax64:
case IR::Opcode::SharedAtomicInc64:
case IR::Opcode::SharedAtomicDec64:
case IR::Opcode::SharedAtomicAnd64:
case IR::Opcode::SharedAtomicOr64:
case IR::Opcode::SharedAtomicXor64:
return true; return true;
default: default:
return false; return false;

42
src/shader_recompiler/ir/passes/shared_memory_to_storage_pass.cpp
View file

@ -17,7 +17,6 @@ static bool IsSharedAccess(const IR::Inst& inst) {
case IR::Opcode::WriteSharedU32: case IR::Opcode::WriteSharedU32:
case IR::Opcode::WriteSharedU64: case IR::Opcode::WriteSharedU64:
case IR::Opcode::SharedAtomicIAdd32: case IR::Opcode::SharedAtomicIAdd32:
case IR::Opcode::SharedAtomicIAdd64:
case IR::Opcode::SharedAtomicISub32: case IR::Opcode::SharedAtomicISub32:
case IR::Opcode::SharedAtomicSMin32: case IR::Opcode::SharedAtomicSMin32:
case IR::Opcode::SharedAtomicUMin32: case IR::Opcode::SharedAtomicUMin32:
@ -28,6 +27,17 @@ static bool IsSharedAccess(const IR::Inst& inst) {
case IR::Opcode::SharedAtomicAnd32: case IR::Opcode::SharedAtomicAnd32:
case IR::Opcode::SharedAtomicOr32: case IR::Opcode::SharedAtomicOr32:
case IR::Opcode::SharedAtomicXor32: case IR::Opcode::SharedAtomicXor32:
case IR::Opcode::SharedAtomicIAdd64:
case IR::Opcode::SharedAtomicISub64:
case IR::Opcode::SharedAtomicSMin64:
case IR::Opcode::SharedAtomicUMin64:
case IR::Opcode::SharedAtomicSMax64:
case IR::Opcode::SharedAtomicUMax64:
case IR::Opcode::SharedAtomicInc64:
case IR::Opcode::SharedAtomicDec64:
case IR::Opcode::SharedAtomicAnd64:
case IR::Opcode::SharedAtomicOr64:
case IR::Opcode::SharedAtomicXor64:
return true; return true;
default: default:
return false; return false;
@ -64,6 +74,16 @@ IR::Type CalculateSharedMemoryTypes(IR::Program& program) {
case IR::Opcode::LoadSharedU64: case IR::Opcode::LoadSharedU64:
case IR::Opcode::WriteSharedU64: case IR::Opcode::WriteSharedU64:
case IR::Opcode::SharedAtomicIAdd64: case IR::Opcode::SharedAtomicIAdd64:
case IR::Opcode::SharedAtomicISub64:
case IR::Opcode::SharedAtomicSMin64:
case IR::Opcode::SharedAtomicUMin64:
case IR::Opcode::SharedAtomicSMax64:
case IR::Opcode::SharedAtomicUMax64:
case IR::Opcode::SharedAtomicInc64:
case IR::Opcode::SharedAtomicDec64:
case IR::Opcode::SharedAtomicAnd64:
case IR::Opcode::SharedAtomicOr64:
case IR::Opcode::SharedAtomicXor64:
used_types |= IR::Type::U64; used_types |= IR::Type::U64;
break; break;
default: default:
@ -119,19 +139,26 @@ void SharedMemoryToStoragePass(IR::Program& program, const RuntimeInfo& runtime_
ir.BufferAtomicIAdd(handle, address, inst.Arg(1), {})); ir.BufferAtomicIAdd(handle, address, inst.Arg(1), {}));
continue; continue;
case IR::Opcode::SharedAtomicISub32: case IR::Opcode::SharedAtomicISub32:
case IR::Opcode::SharedAtomicISub64:
inst.ReplaceUsesWithAndRemove( inst.ReplaceUsesWithAndRemove(
ir.BufferAtomicISub(handle, address, inst.Arg(1), {})); ir.BufferAtomicISub(handle, address, inst.Arg(1), {}));
continue; continue;
case IR::Opcode::SharedAtomicSMin32: case IR::Opcode::SharedAtomicSMin32:
case IR::Opcode::SharedAtomicUMin32: { case IR::Opcode::SharedAtomicUMin32:
const bool is_signed = inst.GetOpcode() == IR::Opcode::SharedAtomicSMin32; case IR::Opcode::SharedAtomicSMin64:
case IR::Opcode::SharedAtomicUMin64: {
const bool is_signed = inst.GetOpcode() == IR::Opcode::SharedAtomicSMin32 ||
inst.GetOpcode() == IR::Opcode::SharedAtomicSMin64;
inst.ReplaceUsesWithAndRemove( inst.ReplaceUsesWithAndRemove(
ir.BufferAtomicIMin(handle, address, inst.Arg(1), is_signed, {})); ir.BufferAtomicIMin(handle, address, inst.Arg(1), is_signed, {}));
continue; continue;
} }
case IR::Opcode::SharedAtomicSMax32: case IR::Opcode::SharedAtomicSMax32:
case IR::Opcode::SharedAtomicUMax32: { case IR::Opcode::SharedAtomicUMax32:
const bool is_signed = inst.GetOpcode() == IR::Opcode::SharedAtomicSMax32; case IR::Opcode::SharedAtomicSMax64:
case IR::Opcode::SharedAtomicUMax64: {
const bool is_signed = inst.GetOpcode() == IR::Opcode::SharedAtomicSMax32 ||
inst.GetOpcode() == IR::Opcode::SharedAtomicSMax64;
inst.ReplaceUsesWithAndRemove( inst.ReplaceUsesWithAndRemove(
ir.BufferAtomicIMax(handle, address, inst.Arg(1), is_signed, {})); ir.BufferAtomicIMax(handle, address, inst.Arg(1), is_signed, {}));
continue; continue;
@ -143,12 +170,15 @@ void SharedMemoryToStoragePass(IR::Program& program, const RuntimeInfo& runtime_
inst.ReplaceUsesWithAndRemove(ir.BufferAtomicDec(handle, address, {})); inst.ReplaceUsesWithAndRemove(ir.BufferAtomicDec(handle, address, {}));
continue; continue;
case IR::Opcode::SharedAtomicAnd32: case IR::Opcode::SharedAtomicAnd32:
case IR::Opcode::SharedAtomicAnd64:
inst.ReplaceUsesWithAndRemove(ir.BufferAtomicAnd(handle, address, inst.Arg(1), {})); inst.ReplaceUsesWithAndRemove(ir.BufferAtomicAnd(handle, address, inst.Arg(1), {}));
continue; continue;
case IR::Opcode::SharedAtomicOr32: case IR::Opcode::SharedAtomicOr32:
case IR::Opcode::SharedAtomicOr64:
inst.ReplaceUsesWithAndRemove(ir.BufferAtomicOr(handle, address, inst.Arg(1), {})); inst.ReplaceUsesWithAndRemove(ir.BufferAtomicOr(handle, address, inst.Arg(1), {}));
continue; continue;
case IR::Opcode::SharedAtomicXor32: case IR::Opcode::SharedAtomicXor32:
case IR::Opcode::SharedAtomicXor64:
inst.ReplaceUsesWithAndRemove(ir.BufferAtomicXor(handle, address, inst.Arg(1), {})); inst.ReplaceUsesWithAndRemove(ir.BufferAtomicXor(handle, address, inst.Arg(1), {}));
continue; continue;
case IR::Opcode::LoadSharedU16: case IR::Opcode::LoadSharedU16:
@ -173,7 +203,7 @@ void SharedMemoryToStoragePass(IR::Program& program, const RuntimeInfo& runtime_
inst.Invalidate(); inst.Invalidate();
break; break;
default: default:
break; UNREACHABLE();
} }
} }
} }