mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-17 17:05:02 +00:00
shader_recompiler: Better branch detection + more opcodes
This commit is contained in:
raphaelthegreat
parent
f624f7749c
commit
02a50265f8
31 changed files with 772 additions and 120 deletions
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@ -38,8 +38,145 @@ void Translator::S_CMP(ConditionOp cond, bool is_signed, const GcnInst& inst) {
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}
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void Translator::S_ANDN2_B64(const GcnInst& inst) {
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// TODO: Actually implement this.
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ir.SetScc(ir.GetVcc());
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// TODO: What if this is used for something other than EXEC masking?
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const auto get_src = [&](const InstOperand& operand) {
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switch (operand.field) {
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case OperandField::VccLo:
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return ir.GetVcc();
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case OperandField::ExecLo:
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return ir.GetExec();
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case OperandField::ScalarGPR:
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return ir.GetThreadBitScalarReg(IR::ScalarReg(operand.code));
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default:
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UNREACHABLE();
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}
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};
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const IR::U1 src0{get_src(inst.src[0])};
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const IR::U1 src1{get_src(inst.src[1])};
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const IR::U1 result{ir.LogicalAnd(src0, ir.LogicalNot(src1))};
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SetDst(inst.dst[0], result);
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ir.SetScc(result);
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}
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void Translator::S_AND_SAVEEXEC_B64(const GcnInst& inst) {
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// This instruction normally operates on 64-bit data (EXEC, VCC, SGPRs)
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// However here we flatten it to 1-bit EXEC and 1-bit VCC. For the destination
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// SGPR we have a special IR opcode for SPGRs that act as thread masks.
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const IR::U1 exec{ir.GetExec()};
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// Mark destination SPGR as an EXEC context. This means we will use 1-bit
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// IR instruction whenever it's loaded.
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ASSERT(inst.dst[0].field == OperandField::ScalarGPR);
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const u32 reg = inst.dst[0].code;
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exec_contexts[reg] = true;
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ir.SetThreadBitScalarReg(IR::ScalarReg(reg), exec);
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// Update EXEC.
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ASSERT(inst.src[0].field == OperandField::VccLo);
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ir.SetExec(ir.LogicalAnd(exec, ir.GetVcc()));
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}
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void Translator::S_MOV_B64(const GcnInst& inst) {
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// TODO: Using VCC as EXEC context.
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if (inst.src[0].field == OperandField::VccLo || inst.dst[0].field == OperandField::VccLo) {
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return;
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}
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const IR::U1 src0{GetSrc(inst.src[0])};
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if (inst.dst[0].field == OperandField::ScalarGPR && inst.src[0].field == OperandField::ExecLo) {
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// Exec context push
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exec_contexts[inst.dst[0].code] = true;
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} else if (inst.dst[0].field == OperandField::ExecLo &&
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inst.src[0].field == OperandField::ScalarGPR) {
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// Exec context pop
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exec_contexts[inst.src[0].code] = false;
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} else if (inst.src[0].field != OperandField::ConstZero) {
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UNREACHABLE();
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}
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SetDst(inst.dst[0], src0);
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}
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void Translator::S_OR_B64(bool negate, const GcnInst& inst) {
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const auto get_src = [&](const InstOperand& operand) {
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switch (operand.field) {
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case OperandField::VccLo:
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return ir.GetVcc();
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case OperandField::ScalarGPR:
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return ir.GetThreadBitScalarReg(IR::ScalarReg(operand.code));
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default:
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UNREACHABLE();
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}
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};
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const IR::U1 src0{get_src(inst.src[0])};
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const IR::U1 src1{get_src(inst.src[1])};
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IR::U1 result = ir.LogicalOr(src0, src1);
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if (negate) {
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result = ir.LogicalNot(result);
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}
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ASSERT(inst.dst[0].field == OperandField::VccLo);
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ir.SetVcc(result);
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ir.SetScc(result);
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}
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void Translator::S_AND_B64(const GcnInst& inst) {
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const auto get_src = [&](const InstOperand& operand) {
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switch (operand.field) {
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case OperandField::VccLo:
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return ir.GetVcc();
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case OperandField::ExecLo:
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return ir.GetExec();
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case OperandField::ScalarGPR:
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return ir.GetThreadBitScalarReg(IR::ScalarReg(operand.code));
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default:
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UNREACHABLE();
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}
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};
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const IR::U1 src0{get_src(inst.src[0])};
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const IR::U1 src1{get_src(inst.src[1])};
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const IR::U1 result = ir.LogicalAnd(src0, src1);
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ASSERT(inst.dst[0].field == OperandField::VccLo);
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ir.SetVcc(result);
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ir.SetScc(result);
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}
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void Translator::S_ADD_I32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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SetDst(inst.dst[0], ir.IAdd(src0, src1));
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// TODO: Overflow flag
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}
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void Translator::S_AND_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 result{ir.BitwiseAnd(src0, src1)};
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
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}
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void Translator::S_LSHR_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 result{ir.ShiftRightLogical(src0, src1)};
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
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}
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void Translator::S_CSELECT_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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SetDst(inst.dst[0], IR::U32{ir.Select(ir.GetScc(), src0, src1)});
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}
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void Translator::S_BFE_U32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 offset{ir.BitwiseAnd(src1, ir.Imm32(0x1F))};
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const IR::U32 count{ir.BitFieldExtract(src1, ir.Imm32(16), ir.Imm32(7))};
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const IR::U32 result{ir.BitFieldExtract(src0, offset, count)};
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
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}
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} // namespace Shader::Gcn
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@ -9,11 +9,15 @@
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namespace Shader::Gcn {
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std::array<bool, IR::NumScalarRegs> Translator::exec_contexts{};
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Translator::Translator(IR::Block* block_, Info& info_)
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: ir{*block_, block_->begin()}, info{info_} {}
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void Translator::EmitPrologue() {
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exec_contexts.fill(false);
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ir.Prologue();
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ir.SetExec(ir.Imm1(true));
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// Initialize user data.
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IR::ScalarReg dst_sreg = IR::ScalarReg::S0;
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@ -54,10 +58,16 @@ void Translator::EmitPrologue() {
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}
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}
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IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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IR::U32F32 value{};
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IR::U1U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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// Input modifiers work on float values.
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force_flt |= operand.input_modifier.abs | operand.input_modifier.neg;
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IR::U1U32F32 value{};
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (exec_contexts[operand.code]) {
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value = ir.GetThreadBitScalarReg(IR::ScalarReg(operand.code));
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}
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if (operand.type == ScalarType::Float32 || force_flt) {
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value = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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} else {
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@ -114,9 +124,15 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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case OperandField::ConstFloatNeg_2_0:
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value = ir.Imm32(-2.0f);
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break;
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case OperandField::ExecLo:
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value = ir.GetExec();
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break;
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case OperandField::VccLo:
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value = ir.GetVccLo();
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break;
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case OperandField::VccHi:
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value = ir.GetVccHi();
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break;
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default:
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UNREACHABLE();
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}
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@ -130,8 +146,8 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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return value;
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}
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void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
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IR::U32F32 result = value;
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void Translator::SetDst(const InstOperand& operand, const IR::U1U32F32& value) {
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IR::U1U32F32 result = value;
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if (operand.output_modifier.multiplier != 0.f) {
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result = ir.FPMul(result, ir.Imm32(operand.output_modifier.multiplier));
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}
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@ -140,14 +156,20 @@ void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
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}
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (value.Type() == IR::Type::U1) {
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return ir.SetThreadBitScalarReg(IR::ScalarReg(operand.code), result);
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}
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return ir.SetScalarReg(IR::ScalarReg(operand.code), result);
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case OperandField::VectorGPR:
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return ir.SetVectorReg(IR::VectorReg(operand.code), result);
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case OperandField::ExecLo:
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return ir.SetExec(result);
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case OperandField::VccLo:
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return ir.SetVccLo(result);
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case OperandField::VccHi:
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return ir.SetVccHi(result);
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case OperandField::M0:
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break; // Ignore for now
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break;
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default:
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UNREACHABLE();
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}
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@ -279,11 +301,32 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::IMAGE_SAMPLE:
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translator.IMAGE_SAMPLE(inst);
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break;
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case Opcode::V_CMP_EQ_U32:
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translator.V_CMP_EQ_U32(inst);
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case Opcode::V_CMP_EQ_I32:
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translator.V_CMP_U32(ConditionOp::EQ, true, false, inst);
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break;
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case Opcode::V_CMPX_GT_U32:
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translator.V_CMPX_GT_U32(inst);
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case Opcode::V_CMP_NE_U32:
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translator.V_CMP_U32(ConditionOp::LG, false, false, inst);
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break;
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case Opcode::V_CMP_EQ_U32:
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translator.V_CMP_U32(ConditionOp::EQ, false, false, inst);
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break;
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case Opcode::V_CMP_F_U32:
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translator.V_CMP_U32(ConditionOp::F, false, false, inst);
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break;
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case Opcode::V_CMP_LT_U32:
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translator.V_CMP_U32(ConditionOp::LT, false, false, inst);
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break;
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case Opcode::V_CMP_GT_U32:
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translator.V_CMP_U32(ConditionOp::GT, false, false, inst);
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break;
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case Opcode::V_CMP_GE_U32:
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translator.V_CMP_U32(ConditionOp::GE, false, false, inst);
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break;
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case Opcode::V_CMP_TRU_U32:
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translator.V_CMP_U32(ConditionOp::TRU, false, false, inst);
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break;
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case Opcode::V_CMP_NEQ_F32:
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translator.V_CMP_F32(ConditionOp::LG, inst);
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break;
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case Opcode::V_CMP_F_F32:
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translator.V_CMP_F32(ConditionOp::F, inst);
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@ -309,6 +352,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::S_CMP_LG_U32:
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translator.S_CMP(ConditionOp::LG, false, inst);
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break;
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case Opcode::S_CMP_EQ_I32:
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translator.S_CMP(ConditionOp::EQ, true, inst);
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break;
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case Opcode::V_CNDMASK_B32:
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translator.V_CNDMASK_B32(inst);
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break;
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@ -348,13 +394,125 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_MIN3_F32:
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translator.V_MIN3_F32(inst);
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break;
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case Opcode::S_NOP:
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case Opcode::V_MADMK_F32:
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translator.V_MADMK_F32(inst);
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break;
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case Opcode::V_CUBEMA_F32:
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translator.V_CUBEMA_F32(inst);
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break;
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case Opcode::V_CUBESC_F32:
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translator.V_CUBESC_F32(inst);
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break;
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case Opcode::V_CUBETC_F32:
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translator.V_CUBETC_F32(inst);
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break;
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case Opcode::V_CUBEID_F32:
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translator.V_CUBEID_F32(inst);
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break;
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case Opcode::V_CVT_U32_F32:
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translator.V_CVT_U32_F32(inst);
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break;
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case Opcode::V_SUBREV_F32:
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translator.V_SUBREV_F32(inst);
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break;
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case Opcode::S_AND_SAVEEXEC_B64:
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translator.S_AND_SAVEEXEC_B64(inst);
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break;
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case Opcode::S_MOV_B64:
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translator.S_MOV_B64(inst);
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break;
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case Opcode::V_SUBREV_I32:
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translator.V_SUBREV_I32(inst);
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break;
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case Opcode::V_CMP_LE_U32:
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translator.V_CMP_U32(ConditionOp::LE, false, false, inst);
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break;
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case Opcode::V_CMP_GT_I32:
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translator.V_CMP_U32(ConditionOp::GT, true, false, inst);
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break;
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case Opcode::V_CMPX_F_U32:
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translator.V_CMP_U32(ConditionOp::F, false, true, inst);
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break;
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case Opcode::V_CMPX_LT_U32:
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translator.V_CMP_U32(ConditionOp::LT, false, true, inst);
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break;
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case Opcode::V_CMPX_EQ_U32:
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translator.V_CMP_U32(ConditionOp::EQ, false, true, inst);
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break;
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case Opcode::V_CMPX_LE_U32:
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translator.V_CMP_U32(ConditionOp::LE, false, true, inst);
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break;
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case Opcode::V_CMPX_GT_U32:
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translator.V_CMP_U32(ConditionOp::GT, false, true, inst);
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break;
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case Opcode::V_CMPX_NE_U32:
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translator.V_CMP_U32(ConditionOp::LG, false, true, inst);
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break;
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case Opcode::V_CMPX_GE_U32:
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translator.V_CMP_U32(ConditionOp::GE, false, true, inst);
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break;
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case Opcode::V_CMPX_TRU_U32:
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translator.V_CMP_U32(ConditionOp::TRU, false, true, inst);
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break;
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case Opcode::S_OR_B64:
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translator.S_OR_B64(false, inst);
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break;
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case Opcode::S_NOR_B64:
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translator.S_OR_B64(true, inst);
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break;
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case Opcode::S_AND_B64:
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translator.S_AND_B64(inst);
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break;
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case Opcode::V_LSHRREV_B32:
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translator.V_LSHRREV_B32(inst);
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break;
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case Opcode::S_ADD_I32:
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translator.S_ADD_I32(inst);
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break;
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case Opcode::V_MUL_LO_I32:
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translator.V_MUL_LO_I32(inst);
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break;
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case Opcode::V_SAD_U32:
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translator.V_SAD_U32(inst);
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break;
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case Opcode::V_BFE_U32:
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translator.V_BFE_U32(inst);
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break;
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case Opcode::V_MAD_I32_I24:
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translator.V_MAD_I32_I24(inst);
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break;
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case Opcode::V_MUL_I32_I24:
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translator.V_MUL_I32_I24(inst);
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break;
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case Opcode::V_SUB_I32:
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translator.V_SUB_I32(inst);
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break;
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case Opcode::V_LSHR_B32:
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translator.V_LSHR_B32(inst);
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break;
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case Opcode::V_ASHRREV_I32:
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translator.V_ASHRREV_I32(inst);
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break;
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case Opcode::V_MAD_U32_U24:
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translator.V_MAD_U32_U24(inst);
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break;
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case Opcode::S_AND_B32:
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translator.S_AND_B32(inst);
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break;
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case Opcode::S_LSHR_B32:
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translator.S_LSHR_B32(inst);
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break;
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case Opcode::S_CSELECT_B32:
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translator.S_CSELECT_B32(inst);
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break;
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case Opcode::S_BFE_U32:
|
||||
translator.S_BFE_U32(inst);
|
||||
break;
|
||||
case Opcode::S_NOP:
|
||||
case Opcode::S_CBRANCH_EXECZ:
|
||||
case Opcode::S_CBRANCH_SCC0:
|
||||
case Opcode::S_CBRANCH_SCC1:
|
||||
case Opcode::S_BRANCH:
|
||||
case Opcode::S_MOV_B64:
|
||||
case Opcode::S_WQM_B64:
|
||||
case Opcode::V_INTERP_P1_F32:
|
||||
case Opcode::S_ENDPGM:
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ enum class ConditionOp : u32 {
|
|||
GE,
|
||||
LT,
|
||||
LE,
|
||||
TRU,
|
||||
};
|
||||
|
||||
class Translator {
|
||||
|
|
@ -37,6 +38,15 @@ public:
|
|||
void S_MUL_I32(const GcnInst& inst);
|
||||
void S_CMP(ConditionOp cond, bool is_signed, const GcnInst& inst);
|
||||
void S_ANDN2_B64(const GcnInst& inst);
|
||||
void S_AND_SAVEEXEC_B64(const GcnInst& inst);
|
||||
void S_MOV_B64(const GcnInst& inst);
|
||||
void S_OR_B64(bool negate, const GcnInst& inst);
|
||||
void S_AND_B64(const GcnInst& inst);
|
||||
void S_ADD_I32(const GcnInst& inst);
|
||||
void S_AND_B32(const GcnInst& inst);
|
||||
void S_LSHR_B32(const GcnInst& inst);
|
||||
void S_CSELECT_B32(const GcnInst& inst);
|
||||
void S_BFE_U32(const GcnInst& inst);
|
||||
|
||||
// Scalar Memory
|
||||
void S_LOAD_DWORD(int num_dwords, const GcnInst& inst);
|
||||
|
|
@ -48,7 +58,6 @@ public:
|
|||
void V_MAC_F32(const GcnInst& inst);
|
||||
void V_CVT_PKRTZ_F16_F32(const GcnInst& inst);
|
||||
void V_MUL_F32(const GcnInst& inst);
|
||||
void V_CMP_EQ_U32(const GcnInst& inst);
|
||||
void V_CNDMASK_B32(const GcnInst& inst);
|
||||
void V_AND_B32(const GcnInst& inst);
|
||||
void V_LSHLREV_B32(const GcnInst& inst);
|
||||
|
|
@ -63,7 +72,6 @@ public:
|
|||
void V_FLOOR_F32(const GcnInst& inst);
|
||||
void V_SUB_F32(const GcnInst& inst);
|
||||
void V_RCP_F32(const GcnInst& inst);
|
||||
void V_CMPX_GT_U32(const GcnInst& inst);
|
||||
void V_FMA_F32(const GcnInst& inst);
|
||||
void V_CMP_F32(ConditionOp op, const GcnInst& inst);
|
||||
void V_MAX_F32(const GcnInst& inst);
|
||||
|
|
@ -74,6 +82,25 @@ public:
|
|||
void V_SQRT_F32(const GcnInst& inst);
|
||||
void V_MIN_F32(const GcnInst& inst);
|
||||
void V_MIN3_F32(const GcnInst& inst);
|
||||
void V_MADMK_F32(const GcnInst& inst);
|
||||
void V_CUBEMA_F32(const GcnInst& inst);
|
||||
void V_CUBESC_F32(const GcnInst& inst);
|
||||
void V_CUBETC_F32(const GcnInst& inst);
|
||||
void V_CUBEID_F32(const GcnInst& inst);
|
||||
void V_CVT_U32_F32(const GcnInst& inst);
|
||||
void V_SUBREV_F32(const GcnInst& inst);
|
||||
void V_SUBREV_I32(const GcnInst& inst);
|
||||
void V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst);
|
||||
void V_LSHRREV_B32(const GcnInst& inst);
|
||||
void V_MUL_LO_I32(const GcnInst& inst);
|
||||
void V_SAD_U32(const GcnInst& inst);
|
||||
void V_BFE_U32(const GcnInst& inst);
|
||||
void V_MAD_I32_I24(const GcnInst& inst);
|
||||
void V_MUL_I32_I24(const GcnInst& inst);
|
||||
void V_SUB_I32(const GcnInst& inst);
|
||||
void V_LSHR_B32(const GcnInst& inst);
|
||||
void V_ASHRREV_I32(const GcnInst& inst);
|
||||
void V_MAD_U32_U24(const GcnInst& inst);
|
||||
|
||||
// Vector Memory
|
||||
void BUFFER_LOAD_FORMAT(u32 num_dwords, bool is_typed, const GcnInst& inst);
|
||||
|
|
@ -94,12 +121,13 @@ public:
|
|||
void EXP(const GcnInst& inst);
|
||||
|
||||
private:
|
||||
IR::U32F32 GetSrc(const InstOperand& operand, bool flt_zero = false);
|
||||
void SetDst(const InstOperand& operand, const IR::U32F32& value);
|
||||
IR::U1U32F32 GetSrc(const InstOperand& operand, bool flt_zero = false);
|
||||
void SetDst(const InstOperand& operand, const IR::U1U32F32& value);
|
||||
|
||||
private:
|
||||
IR::IREmitter ir;
|
||||
Info& info;
|
||||
static std::array<bool, IR::NumScalarRegs> exec_contexts;
|
||||
};
|
||||
|
||||
void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info);
|
||||
|
|
|
|||
|
|
@ -29,17 +29,6 @@ void Translator::V_MUL_F32(const GcnInst& inst) {
|
|||
ir.SetVectorReg(dst_reg, ir.FPMul(GetSrc(inst.src[0], true), GetSrc(inst.src[1], true)));
|
||||
}
|
||||
|
||||
void Translator::V_CMP_EQ_U32(const GcnInst& inst) {
|
||||
const IR::U1 result = ir.IEqual(GetSrc(inst.src[0]), GetSrc(inst.src[1]));
|
||||
if (inst.dst[1].field == OperandField::VccLo) {
|
||||
return ir.SetVcc(result);
|
||||
} else if (inst.dst[1].field == OperandField::ScalarGPR) {
|
||||
const IR::ScalarReg dst_reg{inst.dst[1].code};
|
||||
return ir.SetScalarReg(dst_reg, IR::U32{ir.Select(result, ir.Imm32(1U), ir.Imm32(0U))});
|
||||
}
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
void Translator::V_CNDMASK_B32(const GcnInst& inst) {
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
const IR::ScalarReg flag_reg{inst.src[2].code};
|
||||
|
|
@ -70,9 +59,9 @@ void Translator::V_AND_B32(const GcnInst& inst) {
|
|||
|
||||
void Translator::V_LSHLREV_B32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
ir.SetVectorReg(dst_reg, ir.ShiftLeftLogical(src1, src0));
|
||||
ir.SetVectorReg(dst_reg, ir.ShiftLeftLogical(src1, ir.BitwiseAnd(src0, ir.Imm32(0x1F))));
|
||||
}
|
||||
|
||||
void Translator::V_ADD_I32(const GcnInst& inst) {
|
||||
|
|
@ -148,14 +137,6 @@ void Translator::V_RCP_F32(const GcnInst& inst) {
|
|||
SetDst(inst.dst[0], ir.FPRecip(src0));
|
||||
}
|
||||
|
||||
void Translator::V_CMPX_GT_U32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::U1 result = ir.IGreaterThan(src0, src1, false);
|
||||
ir.SetVcc(result);
|
||||
ir.SetExec(result);
|
||||
}
|
||||
|
||||
void Translator::V_FMA_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
|
|
@ -182,6 +163,8 @@ void Translator::V_CMP_F32(ConditionOp op, const GcnInst& inst) {
|
|||
return ir.FPLessThanEqual(src0, src1);
|
||||
case ConditionOp::GE:
|
||||
return ir.FPGreaterThanEqual(src0, src1);
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
}();
|
||||
ir.SetVcc(result);
|
||||
|
|
@ -231,4 +214,147 @@ void Translator::V_MIN3_F32(const GcnInst& inst) {
|
|||
SetDst(inst.dst[0], ir.FPMin(src0, ir.FPMin(src1, src2)));
|
||||
}
|
||||
|
||||
void Translator::V_MADMK_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 k{GetSrc(inst.src[2], true)};
|
||||
SetDst(inst.dst[0], ir.FPFma(src0, k, src1));
|
||||
}
|
||||
|
||||
void Translator::V_CUBEMA_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], ir.Imm32(1.f));
|
||||
}
|
||||
|
||||
void Translator::V_CUBESC_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], GetSrc(inst.src[0], true));
|
||||
}
|
||||
|
||||
void Translator::V_CUBETC_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], GetSrc(inst.src[1], true));
|
||||
}
|
||||
|
||||
void Translator::V_CUBEID_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], GetSrc(inst.src[2], true));
|
||||
}
|
||||
|
||||
void Translator::V_CVT_U32_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
SetDst(inst.dst[0], ir.ConvertFToU(32, src0));
|
||||
}
|
||||
|
||||
void Translator::V_SUBREV_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
SetDst(inst.dst[0], ir.FPSub(src1, src0));
|
||||
}
|
||||
|
||||
void Translator::V_SUBREV_I32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.ISub(src1, src0));
|
||||
// TODO: Carry-out
|
||||
}
|
||||
|
||||
void Translator::V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::U1 result = [&] {
|
||||
switch (op) {
|
||||
case ConditionOp::F:
|
||||
return ir.Imm1(false);
|
||||
case ConditionOp::TRU:
|
||||
return ir.Imm1(true);
|
||||
case ConditionOp::EQ:
|
||||
return ir.IEqual(src0, src1);
|
||||
case ConditionOp::LG:
|
||||
return ir.INotEqual(src0, src1);
|
||||
case ConditionOp::GT:
|
||||
return ir.IGreaterThan(src0, src1, is_signed);
|
||||
case ConditionOp::LT:
|
||||
return ir.ILessThan(src0, src1, is_signed);
|
||||
case ConditionOp::LE:
|
||||
return ir.ILessThanEqual(src0, src1, is_signed);
|
||||
case ConditionOp::GE:
|
||||
return ir.IGreaterThanEqual(src0, src1, is_signed);
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
}();
|
||||
if (set_exec) {
|
||||
ir.SetExec(result);
|
||||
}
|
||||
switch (inst.dst[1].field) {
|
||||
case OperandField::VccLo:
|
||||
return ir.SetVcc(result);
|
||||
case OperandField::ScalarGPR:
|
||||
return ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[0].code), result);
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
||||
void Translator::V_LSHRREV_B32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.ShiftRightLogical(src1, ir.BitwiseAnd(src0, ir.Imm32(0x1F))));
|
||||
}
|
||||
|
||||
void Translator::V_MUL_LO_I32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.IMul(src0, src1));
|
||||
}
|
||||
|
||||
void Translator::V_SAD_U32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::U32 src2{GetSrc(inst.src[2])};
|
||||
const IR::U32 max{ir.IMax(src0, src1, false)};
|
||||
const IR::U32 min{ir.IMin(src0, src1, false)};
|
||||
SetDst(inst.dst[0], ir.IAdd(ir.ISub(max, min), src2));
|
||||
}
|
||||
|
||||
void Translator::V_BFE_U32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{ir.BitwiseAnd(GetSrc(inst.src[1]), ir.Imm32(0x1F))};
|
||||
const IR::U32 src2{ir.BitwiseAnd(GetSrc(inst.src[2]), ir.Imm32(0x1F))};
|
||||
SetDst(inst.dst[0], ir.BitFieldExtract(src0, src1, src2));
|
||||
}
|
||||
|
||||
void Translator::V_MAD_I32_I24(const GcnInst& inst) {
|
||||
const IR::U32 src0{ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(24), true)};
|
||||
const IR::U32 src1{ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(24), true)};
|
||||
const IR::U32 src2{GetSrc(inst.src[2])};
|
||||
SetDst(inst.dst[0], ir.IAdd(ir.IMul(src0, src1), src2));
|
||||
}
|
||||
|
||||
void Translator::V_MUL_I32_I24(const GcnInst& inst) {
|
||||
const IR::U32 src0{ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(24), true)};
|
||||
const IR::U32 src1{ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(24), true)};
|
||||
SetDst(inst.dst[0], ir.IMul(src0, src1));
|
||||
}
|
||||
|
||||
void Translator::V_SUB_I32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.ISub(src0, src1));
|
||||
}
|
||||
|
||||
void Translator::V_LSHR_B32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.ShiftRightLogical(src0, ir.BitwiseAnd(src1, ir.Imm32(0x1F))));
|
||||
}
|
||||
|
||||
void Translator::V_ASHRREV_I32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.ShiftRightArithmetic(src1, ir.BitwiseAnd(src0, ir.Imm32(0x1F))));
|
||||
}
|
||||
|
||||
void Translator::V_MAD_U32_U24(const GcnInst& inst) {
|
||||
// TODO:
|
||||
V_MAD_I32_I24(inst);
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@ namespace Shader::Gcn {
|
|||
void Translator::V_INTERP_P2_F32(const GcnInst& inst) {
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
auto& attr = info.ps_inputs.at(inst.control.vintrp.attr);
|
||||
attr.semantic = inst.control.vintrp.attr;
|
||||
const IR::Attribute attrib{IR::Attribute::Param0 + attr.param_index};
|
||||
ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue