From 0845fe2b2b7c6c7bc47ee0bcb44165e144a8b32a Mon Sep 17 00:00:00 2001 From: offtkp Date: Sun, 6 Jul 2025 22:10:09 +0300 Subject: [PATCH] Fix V_ADDC_U32 carry-out edge cases --- src/shader_recompiler/frontend/translate/vector_alu.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp index 54f1088f2..db82b9a8b 100644 --- a/src/shader_recompiler/frontend/translate/vector_alu.cpp +++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp @@ -623,12 +623,13 @@ void Translator::V_ADDC_U32(const GcnInst& inst) { const IR::U32 src0{GetSrc(inst.src[0])}; const IR::U32 src1{GetSrc(inst.src[1])}; const IR::U32 carry{GetCarryIn(inst)}; - const IR::U32 result{ir.IAdd(ir.IAdd(src0, src1), carry)}; + const IR::U32 temp{ir.IAdd(src0, src1)}; + const IR::U32 result{ir.IAdd(temp, carry)}; SetDst(inst.dst[0], result); - const IR::U1 less_src0{ir.ILessThan(result, src0, false)}; - const IR::U1 less_src1{ir.ILessThan(result, src1, false)}; - const IR::U1 did_overflow{ir.LogicalOr(less_src0, less_src1)}; + const IR::U1 less_1{ir.ILessThan(temp, src0, false)}; + const IR::U1 less_2{ir.ILessThan(result, carry, false)}; + const IR::U1 did_overflow{ir.LogicalOr(less_1, less_2)}; SetCarryOut(inst, did_overflow); }