Mirrors/shadPS4
1
0
Fork 0
mirror of https://github.com/shadps4-emu/shadPS4.git synced 2025-07-04 16:16:20 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 5

Merge pull request #293 from shadps4-emu/misc-fixes3

Browse source 
Various linux fixes
This commit is contained in:
georgemoralis 2024-07-15 15:25:20 +03:00 • committed by GitHub
commit 0de914995f
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
14 changed files with 172 additions and 165 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/shader_recompiler/frontend/translate/export.cpp
View file

@ -7,7 +7,7 @@
namespace Shader::Gcn {
void Translator::EXP(const GcnInst& inst) {
if (ir.block->has_multiple_predecessors) {
if (ir.block->has_multiple_predecessors && info.stage == Stage::Fragment) {
LOG_WARNING(Render_Recompiler, "An ambiguous export appeared in translation");
ir.Discard(ir.LogicalNot(ir.GetExec()));
}

13
src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp
View file

@ -173,7 +173,7 @@ public:
}
template <typename Type>
IR::Value ReadVariable(Type variable, IR::Block* root_block) {
IR::Value ReadVariable(Type variable, IR::Block* root_block, bool is_thread_bit = false) {
boost::container::small_vector<ReadState<Type>, 64> stack{
ReadState<Type>(nullptr),
ReadState<Type>(root_block),
@ -201,7 +201,7 @@ public:
} else if (!block->IsSsaSealed()) {
// Incomplete CFG
IR::Inst* phi{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)};
phi->SetFlags(IR::TypeOf(UndefOpcode(variable)));
phi->SetFlags(is_thread_bit ? IR::Type::U1 : IR::TypeOf(UndefOpcode(variable)));
incomplete_phis[block].insert_or_assign(variable, phi);
stack.back().result = IR::Value{&*phi};
@ -214,7 +214,7 @@ public:
} else {
// Break potential cycles with operandless phi
IR::Inst* const phi{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)};
phi->SetFlags(IR::TypeOf(UndefOpcode(variable)));
phi->SetFlags(is_thread_bit ? IR::Type::U1 : IR::TypeOf(UndefOpcode(variable)));
WriteVariable(variable, block, IR::Value{phi});
@ -263,7 +263,9 @@ private:
template <typename Type>
IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) {
for (IR::Block* const imm_pred : block->ImmPredecessors()) {
phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred));
const bool is_thread_bit =
std::is_same_v<Type, IR::ScalarReg> && phi.Flags<IR::Type>() == IR::Type::U1;
phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred, is_thread_bit));
}
return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable));
}
@ -346,7 +348,8 @@ void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
case IR::Opcode::GetThreadBitScalarReg:
case IR::Opcode::GetScalarRegister: {
const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
inst.ReplaceUsesWith(pass.ReadVariable(reg, block));
inst.ReplaceUsesWith(
pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg));
break;
}
case IR::Opcode::GetVectorRegister: {