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shader_recompiler: Implement data share append and consume operations (#814)
* shader_recompiler: Add more format swap modes * texture_cache: Handle stencil texture reads * emulator: Support loading font library * readme: Add thanks section * shader_recompiler: Constant buffers as integers * shader_recompiler: Typed buffers as integers * shader_recompiler: Separate thread bit scalars * We can assume guest shader never mixes them with normal sgprs. This helps avoid errors where ssa could view an sgpr write dominating a thread bit read, due to how control flow is structurized, even though its not possible in actual control flow * shader_recompiler: Implement data append/consume operations * clang format * buffer_cache: Simplify invalidation scheme * video_core: Remove some invalidation remnants * adjust
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649527a235
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34 changed files with 512 additions and 272 deletions
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@ -43,6 +43,10 @@ void Translator::EmitDataShare(const GcnInst& inst) {
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return DS_MIN_U32(inst, false, true);
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case Opcode::DS_MAX_RTN_U32:
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return DS_MAX_U32(inst, false, true);
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case Opcode::DS_APPEND:
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return DS_APPEND(inst);
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case Opcode::DS_CONSUME:
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return DS_CONSUME(inst);
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default:
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LogMissingOpcode(inst);
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}
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@ -192,4 +196,18 @@ void Translator::V_WRITELANE_B32(const GcnInst& inst) {
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ir.SetVectorReg(dst, ir.WriteLane(old_value, value, lane));
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}
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void Translator::DS_APPEND(const GcnInst& inst) {
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const u32 inst_offset = inst.control.ds.offset0;
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const IR::U32 gds_offset = ir.IAdd(ir.GetM0(), ir.Imm32(inst_offset));
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const IR::U32 prev = ir.DataAppend(gds_offset);
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SetDst(inst.dst[0], prev);
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}
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void Translator::DS_CONSUME(const GcnInst& inst) {
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const u32 inst_offset = inst.control.ds.offset0;
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const IR::U32 gds_offset = ir.IAdd(ir.GetM0(), ir.Imm32(inst_offset));
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const IR::U32 prev = ir.DataConsume(gds_offset);
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SetDst(inst.dst[0], prev);
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}
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} // namespace Shader::Gcn
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