mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-24 12:25:00 +00:00
shader_recompiler: Implement data share append and consume operations (#814)
* shader_recompiler: Add more format swap modes * texture_cache: Handle stencil texture reads * emulator: Support loading font library * readme: Add thanks section * shader_recompiler: Constant buffers as integers * shader_recompiler: Typed buffers as integers * shader_recompiler: Separate thread bit scalars * We can assume guest shader never mixes them with normal sgprs. This helps avoid errors where ssa could view an sgpr write dominating a thread bit read, due to how control flow is structurized, even though its not possible in actual control flow * shader_recompiler: Implement data append/consume operations * clang format * buffer_cache: Simplify invalidation scheme * video_core: Remove some invalidation remnants * adjust
This commit is contained in:
TheTurtle
GitHub
parent
649527a235
commit
13743b27fc
34 changed files with 512 additions and 272 deletions
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@ -147,6 +147,7 @@ public:
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/// Intrusively store the value of a register in the block.
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std::array<Value, NumScalarRegs> ssa_sreg_values;
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std::array<Value, NumScalarRegs> ssa_sbit_values;
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std::array<Value, NumVectorRegs> ssa_vreg_values;
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bool has_multiple_predecessors{false};
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@ -313,21 +313,21 @@ U32 IREmitter::ReadConst(const Value& base, const U32& offset) {
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return Inst<U32>(Opcode::ReadConst, base, offset);
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}
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F32 IREmitter::ReadConstBuffer(const Value& handle, const U32& index) {
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return Inst<F32>(Opcode::ReadConstBuffer, handle, index);
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U32 IREmitter::ReadConstBuffer(const Value& handle, const U32& index) {
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return Inst<U32>(Opcode::ReadConstBuffer, handle, index);
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}
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Value IREmitter::LoadBuffer(int num_dwords, const Value& handle, const Value& address,
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BufferInstInfo info) {
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switch (num_dwords) {
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case 1:
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return Inst(Opcode::LoadBufferF32, Flags{info}, handle, address);
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return Inst(Opcode::LoadBufferU32, Flags{info}, handle, address);
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case 2:
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return Inst(Opcode::LoadBufferF32x2, Flags{info}, handle, address);
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return Inst(Opcode::LoadBufferU32x2, Flags{info}, handle, address);
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case 3:
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return Inst(Opcode::LoadBufferF32x3, Flags{info}, handle, address);
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return Inst(Opcode::LoadBufferU32x3, Flags{info}, handle, address);
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case 4:
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return Inst(Opcode::LoadBufferF32x4, Flags{info}, handle, address);
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return Inst(Opcode::LoadBufferU32x4, Flags{info}, handle, address);
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default:
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UNREACHABLE_MSG("Invalid number of dwords {}", num_dwords);
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}
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@ -341,17 +341,16 @@ void IREmitter::StoreBuffer(int num_dwords, const Value& handle, const Value& ad
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const Value& data, BufferInstInfo info) {
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switch (num_dwords) {
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case 1:
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Inst(data.Type() == Type::F32 ? Opcode::StoreBufferF32 : Opcode::StoreBufferU32,
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Flags{info}, handle, address, data);
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Inst(Opcode::StoreBufferU32, Flags{info}, handle, address, data);
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break;
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case 2:
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Inst(Opcode::StoreBufferF32x2, Flags{info}, handle, address, data);
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Inst(Opcode::StoreBufferU32x2, Flags{info}, handle, address, data);
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break;
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case 3:
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Inst(Opcode::StoreBufferF32x3, Flags{info}, handle, address, data);
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Inst(Opcode::StoreBufferU32x3, Flags{info}, handle, address, data);
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break;
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case 4:
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Inst(Opcode::StoreBufferF32x4, Flags{info}, handle, address, data);
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Inst(Opcode::StoreBufferU32x4, Flags{info}, handle, address, data);
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break;
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default:
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UNREACHABLE_MSG("Invalid number of dwords {}", num_dwords);
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@ -410,6 +409,14 @@ void IREmitter::StoreBufferFormat(const Value& handle, const Value& address, con
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Inst(Opcode::StoreBufferFormatF32, Flags{info}, handle, address, data);
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}
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U32 IREmitter::DataAppend(const U32& counter) {
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return Inst<U32>(Opcode::DataAppend, counter, Imm32(0));
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}
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U32 IREmitter::DataConsume(const U32& counter) {
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return Inst<U32>(Opcode::DataConsume, counter, Imm32(0));
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}
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U32 IREmitter::LaneId() {
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return Inst<U32>(Opcode::LaneId);
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}
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@ -90,7 +90,7 @@ public:
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[[nodiscard]] U32 SharedAtomicIMax(const U32& address, const U32& data, bool is_signed);
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[[nodiscard]] U32 ReadConst(const Value& base, const U32& offset);
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[[nodiscard]] F32 ReadConstBuffer(const Value& handle, const U32& index);
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[[nodiscard]] U32 ReadConstBuffer(const Value& handle, const U32& index);
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[[nodiscard]] Value LoadBuffer(int num_dwords, const Value& handle, const Value& address,
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BufferInstInfo info);
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@ -120,6 +120,8 @@ public:
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[[nodiscard]] Value BufferAtomicSwap(const Value& handle, const Value& address,
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const Value& value, BufferInstInfo info);
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[[nodiscard]] U32 DataAppend(const U32& counter);
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[[nodiscard]] U32 DataConsume(const U32& counter);
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[[nodiscard]] U32 LaneId();
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[[nodiscard]] U32 WarpId();
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[[nodiscard]] U32 QuadShuffle(const U32& value, const U32& index);
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@ -51,12 +51,11 @@ bool Inst::MayHaveSideEffects() const noexcept {
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case Opcode::Discard:
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case Opcode::DiscardCond:
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case Opcode::SetAttribute:
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case Opcode::StoreBufferF32:
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case Opcode::StoreBufferF32x2:
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case Opcode::StoreBufferF32x3:
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case Opcode::StoreBufferF32x4:
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case Opcode::StoreBufferFormatF32:
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case Opcode::StoreBufferU32:
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case Opcode::StoreBufferU32x2:
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case Opcode::StoreBufferU32x3:
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case Opcode::StoreBufferU32x4:
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case Opcode::StoreBufferFormatF32:
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case Opcode::BufferAtomicIAdd32:
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case Opcode::BufferAtomicSMin32:
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case Opcode::BufferAtomicUMin32:
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@ -68,6 +67,8 @@ bool Inst::MayHaveSideEffects() const noexcept {
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case Opcode::BufferAtomicOr32:
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case Opcode::BufferAtomicXor32:
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case Opcode::BufferAtomicSwap32:
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case Opcode::DataAppend:
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case Opcode::DataConsume:
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case Opcode::WriteSharedU128:
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case Opcode::WriteSharedU64:
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case Opcode::WriteSharedU32:
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@ -17,8 +17,7 @@ OPCODE(DiscardCond, Void, U1,
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// Constant memory operations
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OPCODE(ReadConst, U32, U32x2, U32, )
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OPCODE(ReadConstBuffer, F32, Opaque, U32, )
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OPCODE(ReadConstBufferU32, U32, Opaque, U32, )
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OPCODE(ReadConstBuffer, U32, Opaque, U32, )
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// Barriers
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OPCODE(Barrier, Void, )
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@ -77,21 +76,19 @@ OPCODE(UndefU32, U32,
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OPCODE(UndefU64, U64, )
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// Buffer operations
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OPCODE(LoadBufferF32, F32, Opaque, Opaque, )
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OPCODE(LoadBufferF32x2, F32x2, Opaque, Opaque, )
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OPCODE(LoadBufferF32x3, F32x3, Opaque, Opaque, )
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OPCODE(LoadBufferF32x4, F32x4, Opaque, Opaque, )
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OPCODE(LoadBufferFormatF32, F32x4, Opaque, Opaque, )
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OPCODE(LoadBufferU32, U32, Opaque, Opaque, )
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OPCODE(StoreBufferF32, Void, Opaque, Opaque, F32, )
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OPCODE(StoreBufferF32x2, Void, Opaque, Opaque, F32x2, )
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OPCODE(StoreBufferF32x3, Void, Opaque, Opaque, F32x3, )
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OPCODE(StoreBufferF32x4, Void, Opaque, Opaque, F32x4, )
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OPCODE(StoreBufferFormatF32, Void, Opaque, Opaque, F32x4, )
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OPCODE(LoadBufferU32x2, U32x2, Opaque, Opaque, )
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OPCODE(LoadBufferU32x3, U32x3, Opaque, Opaque, )
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OPCODE(LoadBufferU32x4, U32x4, Opaque, Opaque, )
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OPCODE(LoadBufferFormatF32, F32x4, Opaque, Opaque, )
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OPCODE(StoreBufferU32, Void, Opaque, Opaque, U32, )
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OPCODE(StoreBufferU32x2, Void, Opaque, Opaque, U32x2, )
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OPCODE(StoreBufferU32x3, Void, Opaque, Opaque, U32x3, )
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OPCODE(StoreBufferU32x4, Void, Opaque, Opaque, U32x4, )
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OPCODE(StoreBufferFormatF32, Void, Opaque, Opaque, U32x4, )
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// Buffer atomic operations
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OPCODE(BufferAtomicIAdd32, U32, Opaque, Opaque, U32 )
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OPCODE(BufferAtomicIAdd32, U32, Opaque, Opaque, U32 )
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OPCODE(BufferAtomicSMin32, U32, Opaque, Opaque, U32 )
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OPCODE(BufferAtomicUMin32, U32, Opaque, Opaque, U32 )
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OPCODE(BufferAtomicSMax32, U32, Opaque, Opaque, U32 )
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@ -101,7 +98,7 @@ OPCODE(BufferAtomicDec32, U32, Opaq
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OPCODE(BufferAtomicAnd32, U32, Opaque, Opaque, U32, )
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OPCODE(BufferAtomicOr32, U32, Opaque, Opaque, U32, )
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OPCODE(BufferAtomicXor32, U32, Opaque, Opaque, U32, )
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OPCODE(BufferAtomicSwap32, U32, Opaque, Opaque, U32, )
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OPCODE(BufferAtomicSwap32, U32, Opaque, Opaque, U32, )
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// Vector utility
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OPCODE(CompositeConstructU32x2, U32x2, U32, U32, )
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@ -345,3 +342,5 @@ OPCODE(QuadShuffle, U32, U32,
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OPCODE(ReadFirstLane, U32, U32, )
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OPCODE(ReadLane, U32, U32, U32 )
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OPCODE(WriteLane, U32, U32, U32, U32 )
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OPCODE(DataAppend, U32, U32, U32 )
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OPCODE(DataConsume, U32, U32, U32 )
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@ -3,7 +3,6 @@
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#include <algorithm>
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#include <boost/container/small_vector.hpp>
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#include "common/alignment.h"
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#include "shader_recompiler/info.h"
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#include "shader_recompiler/ir/basic_block.h"
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#include "shader_recompiler/ir/breadth_first_search.h"
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@ -42,11 +41,10 @@ bool IsBufferAtomic(const IR::Inst& inst) {
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bool IsBufferStore(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::StoreBufferF32:
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case IR::Opcode::StoreBufferF32x2:
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case IR::Opcode::StoreBufferF32x3:
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case IR::Opcode::StoreBufferF32x4:
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case IR::Opcode::StoreBufferU32:
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case IR::Opcode::StoreBufferU32x2:
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case IR::Opcode::StoreBufferU32x3:
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case IR::Opcode::StoreBufferU32x4:
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return true;
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default:
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return IsBufferAtomic(inst);
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@ -55,25 +53,28 @@ bool IsBufferStore(const IR::Inst& inst) {
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bool IsBufferInstruction(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::LoadBufferF32:
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case IR::Opcode::LoadBufferF32x2:
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case IR::Opcode::LoadBufferF32x3:
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case IR::Opcode::LoadBufferF32x4:
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case IR::Opcode::LoadBufferU32:
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case IR::Opcode::LoadBufferU32x2:
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case IR::Opcode::LoadBufferU32x3:
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case IR::Opcode::LoadBufferU32x4:
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case IR::Opcode::ReadConstBuffer:
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case IR::Opcode::ReadConstBufferU32:
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return true;
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default:
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return IsBufferStore(inst);
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}
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}
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bool IsDataRingInstruction(const IR::Inst& inst) {
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return inst.GetOpcode() == IR::Opcode::DataAppend ||
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inst.GetOpcode() == IR::Opcode::DataConsume;
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}
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bool IsTextureBufferInstruction(const IR::Inst& inst) {
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return inst.GetOpcode() == IR::Opcode::LoadBufferFormatF32 ||
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inst.GetOpcode() == IR::Opcode::StoreBufferFormatF32;
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}
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static bool UseFP16(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat num_format) {
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bool UseFP16(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat num_format) {
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switch (num_format) {
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case AmdGpu::NumberFormat::Float:
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switch (data_format) {
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@ -98,19 +99,15 @@ static bool UseFP16(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat num_for
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IR::Type BufferDataType(const IR::Inst& inst, AmdGpu::NumberFormat num_format) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::LoadBufferF32:
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case IR::Opcode::LoadBufferF32x2:
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case IR::Opcode::LoadBufferF32x3:
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case IR::Opcode::LoadBufferF32x4:
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case IR::Opcode::ReadConstBuffer:
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case IR::Opcode::StoreBufferF32:
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case IR::Opcode::StoreBufferF32x2:
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case IR::Opcode::StoreBufferF32x3:
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case IR::Opcode::StoreBufferF32x4:
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return IR::Type::F32;
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case IR::Opcode::LoadBufferU32:
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case IR::Opcode::ReadConstBufferU32:
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case IR::Opcode::LoadBufferU32x2:
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case IR::Opcode::LoadBufferU32x3:
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case IR::Opcode::LoadBufferU32x4:
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case IR::Opcode::StoreBufferU32:
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case IR::Opcode::StoreBufferU32x2:
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case IR::Opcode::StoreBufferU32x3:
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case IR::Opcode::StoreBufferU32x4:
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case IR::Opcode::ReadConstBuffer:
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case IR::Opcode::BufferAtomicIAdd32:
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case IR::Opcode::BufferAtomicSwap32:
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return IR::Type::U32;
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@ -191,6 +188,10 @@ public:
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u32 Add(const BufferResource& desc) {
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const u32 index{Add(buffer_resources, desc, [&desc](const auto& existing) {
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// Only one GDS binding can exist.
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if (desc.is_gds_buffer && existing.is_gds_buffer) {
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return true;
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}
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return desc.sgpr_base == existing.sgpr_base &&
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desc.dword_offset == existing.dword_offset &&
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desc.inline_cbuf == existing.inline_cbuf;
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@ -399,8 +400,7 @@ void PatchBufferInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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ASSERT(!buffer.swizzle_enable && !buffer.add_tid_enable);
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// Address of constant buffer reads can be calculated at IR emittion time.
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if (inst.GetOpcode() == IR::Opcode::ReadConstBuffer ||
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inst.GetOpcode() == IR::Opcode::ReadConstBufferU32) {
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if (inst.GetOpcode() == IR::Opcode::ReadConstBuffer) {
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return;
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}
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@ -609,6 +609,51 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
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}
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}
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void PatchDataRingInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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Descriptors& descriptors) {
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// Insert gds binding in the shader if it doesn't exist already.
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// The buffer is used for append/consume counters.
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constexpr static AmdGpu::Buffer GdsSharp{.base_address = 1};
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const u32 binding = descriptors.Add(BufferResource{
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.used_types = IR::Type::U32,
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.inline_cbuf = GdsSharp,
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.is_gds_buffer = true,
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.is_written = true,
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});
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const auto pred = [](const IR::Inst* inst) -> std::optional<const IR::Inst*> {
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if (inst->GetOpcode() == IR::Opcode::GetUserData) {
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return inst;
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}
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return std::nullopt;
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};
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// Attempt to deduce the GDS address of counter at compile time.
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const u32 gds_addr = [&] {
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const IR::Value& gds_offset = inst.Arg(0);
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if (gds_offset.IsImmediate()) {
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// Nothing to do, offset is known.
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return gds_offset.U32() & 0xFFFF;
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}
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const auto result = IR::BreadthFirstSearch(&inst, pred);
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ASSERT_MSG(result, "Unable to track M0 source");
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// M0 must be set by some user data register.
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const IR::Inst* prod = gds_offset.InstRecursive();
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const u32 ud_reg = u32(result.value()->Arg(0).ScalarReg());
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u32 m0_val = info.user_data[ud_reg] >> 16;
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if (prod->GetOpcode() == IR::Opcode::IAdd32) {
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m0_val += prod->Arg(1).U32();
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}
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return m0_val & 0xFFFF;
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}();
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// Patch instruction.
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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inst.SetArg(0, ir.Imm32(gds_addr >> 2));
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inst.SetArg(1, ir.Imm32(binding));
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}
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void ResourceTrackingPass(IR::Program& program) {
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// Iterate resource instructions and patch them after finding the sharp.
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auto& info = program.info;
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@ -625,6 +670,10 @@ void ResourceTrackingPass(IR::Program& program) {
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}
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if (IsImageInstruction(inst)) {
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PatchImageInstruction(*block, inst, info, descriptors);
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continue;
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}
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if (IsDataRingInstruction(inst)) {
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PatchDataRingInstruction(*block, inst, info, descriptors);
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}
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}
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}
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@ -44,8 +44,17 @@ struct GotoVariable : FlagTag {
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u32 index;
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};
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using Variant = std::variant<IR::ScalarReg, IR::VectorReg, GotoVariable, SccFlagTag, ExecFlagTag,
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VccFlagTag, VccLoTag, VccHiTag, M0Tag>;
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struct ThreadBitScalar : FlagTag {
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ThreadBitScalar() = default;
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explicit ThreadBitScalar(IR::ScalarReg sgpr_) : sgpr{sgpr_} {}
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auto operator<=>(const ThreadBitScalar&) const noexcept = default;
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IR::ScalarReg sgpr;
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};
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using Variant = std::variant<IR::ScalarReg, IR::VectorReg, GotoVariable, ThreadBitScalar,
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SccFlagTag, ExecFlagTag, VccFlagTag, VccLoTag, VccHiTag, M0Tag>;
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using ValueMap = std::unordered_map<IR::Block*, IR::Value>;
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struct DefTable {
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@ -70,6 +79,13 @@ struct DefTable {
|
|||
goto_vars[variable.index].insert_or_assign(block, value);
|
||||
}
|
||||
|
||||
const IR::Value& Def(IR::Block* block, ThreadBitScalar variable) {
|
||||
return block->ssa_sreg_values[RegIndex(variable.sgpr)];
|
||||
}
|
||||
void SetDef(IR::Block* block, ThreadBitScalar variable, const IR::Value& value) {
|
||||
block->ssa_sreg_values[RegIndex(variable.sgpr)] = value;
|
||||
}
|
||||
|
||||
const IR::Value& Def(IR::Block* block, SccFlagTag) {
|
||||
return scc_flag[block];
|
||||
}
|
||||
|
|
@ -173,7 +189,7 @@ public:
|
|||
}
|
||||
|
||||
template <typename Type>
|
||||
IR::Value ReadVariable(Type variable, IR::Block* root_block, bool is_thread_bit = false) {
|
||||
IR::Value ReadVariable(Type variable, IR::Block* root_block) {
|
||||
boost::container::small_vector<ReadState<Type>, 64> stack{
|
||||
ReadState<Type>(nullptr),
|
||||
ReadState<Type>(root_block),
|
||||
|
|
@ -201,7 +217,7 @@ public:
|
|||
} else if (!block->IsSsaSealed()) {
|
||||
// Incomplete CFG
|
||||
IR::Inst* phi{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)};
|
||||
phi->SetFlags(is_thread_bit ? IR::Type::U1 : IR::TypeOf(UndefOpcode(variable)));
|
||||
phi->SetFlags(IR::TypeOf(UndefOpcode(variable)));
|
||||
|
||||
incomplete_phis[block].insert_or_assign(variable, phi);
|
||||
stack.back().result = IR::Value{&*phi};
|
||||
|
|
@ -214,7 +230,7 @@ public:
|
|||
} else {
|
||||
// Break potential cycles with operandless phi
|
||||
IR::Inst* const phi{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)};
|
||||
phi->SetFlags(is_thread_bit ? IR::Type::U1 : IR::TypeOf(UndefOpcode(variable)));
|
||||
phi->SetFlags(IR::TypeOf(UndefOpcode(variable)));
|
||||
|
||||
WriteVariable(variable, block, IR::Value{phi});
|
||||
|
||||
|
|
@ -263,9 +279,7 @@ private:
|
|||
template <typename Type>
|
||||
IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) {
|
||||
for (IR::Block* const imm_pred : block->ImmPredecessors()) {
|
||||
const bool is_thread_bit =
|
||||
std::is_same_v<Type, IR::ScalarReg> && phi.Flags<IR::Type>() == IR::Type::U1;
|
||||
phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred, is_thread_bit));
|
||||
phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred));
|
||||
}
|
||||
return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable));
|
||||
}
|
||||
|
|
@ -313,7 +327,11 @@ private:
|
|||
void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
|
||||
const IR::Opcode opcode{inst.GetOpcode()};
|
||||
switch (opcode) {
|
||||
case IR::Opcode::SetThreadBitScalarReg:
|
||||
case IR::Opcode::SetThreadBitScalarReg: {
|
||||
const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
|
||||
pass.WriteVariable(ThreadBitScalar{reg}, block, inst.Arg(1));
|
||||
break;
|
||||
}
|
||||
case IR::Opcode::SetScalarRegister: {
|
||||
const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
|
||||
pass.WriteVariable(reg, block, inst.Arg(1));
|
||||
|
|
@ -345,11 +363,15 @@ void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
|
|||
case IR::Opcode::SetM0:
|
||||
pass.WriteVariable(M0Tag{}, block, inst.Arg(0));
|
||||
break;
|
||||
case IR::Opcode::GetThreadBitScalarReg:
|
||||
case IR::Opcode::GetThreadBitScalarReg: {
|
||||
const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
|
||||
const IR::Value value = pass.ReadVariable(ThreadBitScalar{reg}, block);
|
||||
inst.ReplaceUsesWith(value);
|
||||
break;
|
||||
}
|
||||
case IR::Opcode::GetScalarRegister: {
|
||||
const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
|
||||
const bool thread_bit = opcode == IR::Opcode::GetThreadBitScalarReg;
|
||||
const IR::Value value = pass.ReadVariable(reg, block, thread_bit);
|
||||
const IR::Value value = pass.ReadVariable(reg, block);
|
||||
inst.ReplaceUsesWith(value);
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue