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Fix V_ADDC_U32 carry-out edge cases (#3200)

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* Fix V_ADDC_U32 carry-out edge cases

* Use IAddCarry instead
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Paris Oplopoios 2025-07-07 12:44:06 +03:00 • committed by GitHub
parent 5eef2fd28a
commit 146e81a56a
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1 changed files with 8 additions and 5 deletions
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13
src/shader_recompiler/frontend/translate/vector_alu.cpp
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@ -623,12 +623,15 @@ void Translator::V_ADDC_U32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
const IR::U32 carry{GetCarryIn(inst)};
const IR::U32 result{ir.IAdd(ir.IAdd(src0, src1), carry)};
SetDst(inst.dst[0], result);
const IR::Value tmp1{ir.IAddCary(src0, src1)};
const IR::U32 result1{ir.CompositeExtract(tmp1, 0)};
const IR::U32 carry_out1{ir.CompositeExtract(tmp1, 1)};
const IR::Value tmp2{ir.IAddCary(result1, carry)};
const IR::U32 result2{ir.CompositeExtract(tmp2, 0)};
const IR::U32 carry_out2{ir.CompositeExtract(tmp2, 1)};
SetDst(inst.dst[0], result2);
const IR::U1 less_src0{ir.ILessThan(result, src0, false)};
const IR::U1 less_src1{ir.ILessThan(result, src1, false)};
const IR::U1 did_overflow{ir.LogicalOr(less_src0, less_src1)};
const IR::U1 did_overflow{ir.INotEqual(ir.BitwiseOr(carry_out1, carry_out2), ir.Imm32(0))};
SetCarryOut(inst, did_overflow);
}