mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-18 17:34:52 +00:00
video_core: Crucial buffer cache fixes + proper GPU clears (#414)
* translator: Use templates for stronger type guarantees * spirv: Define buffer offsets upfront * Saves a lot of shader instructions * buffer_cache: Use dynamic vertex input when available * Fixes issues when games like dark souls rebind vertex buffers with different stride * externals: Update boost * spirv: Use runtime array for ssbos * ssbos can be large and typically their size will vary, especially in generic copy/clear cs shaders * fs: Lock when doing case insensitive search * Dark Souls does fs lookups from different threads * texture_cache: More precise invalidation from compute * Fixes unrelated render targets being cleared * texture_cache: Use hashes for protect gpu modified images from reupload * translator: Treat V_CNDMASK as float * Sometimes it can have input modifiers. Worst this will cause is some extra calls to uintBitsToFloat and opposite. But most often this is used as float anyway * translator: Small optimization for V_SAD_U32 * Fix review * clang format
This commit is contained in:
TheTurtle
GitHub
parent
dfcfd62d4f
commit
1fb0da9b89
23 changed files with 372 additions and 346 deletions
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@ -73,101 +73,190 @@ void Translator::EmitPrologue() {
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}
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}
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template <>
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IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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IR::U32F32 value{};
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template <typename T>
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T Translator::GetSrc(const InstOperand& operand) {
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constexpr bool is_float = std::is_same_v<T, IR::F32>;
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const bool is_float = operand.type == ScalarType::Float32 || force_flt;
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const auto get_imm = [&](auto value) -> T {
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if constexpr (is_float) {
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return ir.Imm32(std::bit_cast<float>(value));
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} else {
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return ir.Imm32(std::bit_cast<u32>(value));
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}
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};
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T value{};
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (is_float) {
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value = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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} else {
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value = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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}
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value = ir.GetScalarReg<T>(IR::ScalarReg(operand.code));
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break;
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case OperandField::VectorGPR:
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if (is_float) {
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value = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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} else {
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value = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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}
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value = ir.GetVectorReg<T>(IR::VectorReg(operand.code));
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break;
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case OperandField::ConstZero:
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if (is_float) {
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value = ir.Imm32(0.f);
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} else {
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value = ir.Imm32(0U);
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}
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value = get_imm(0U);
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break;
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case OperandField::SignedConstIntPos:
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ASSERT(!force_flt);
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value = ir.Imm32(operand.code - SignedConstIntPosMin + 1);
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value = get_imm(operand.code - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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ASSERT(!force_flt);
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value = ir.Imm32(-s32(operand.code) + SignedConstIntNegMin - 1);
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value = get_imm(-s32(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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if (is_float) {
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value = ir.Imm32(std::bit_cast<float>(operand.code));
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} else {
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value = ir.Imm32(operand.code);
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}
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value = get_imm(operand.code);
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break;
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case OperandField::ConstFloatPos_1_0:
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if (is_float) {
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value = ir.Imm32(1.f);
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} else {
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value = ir.Imm32(std::bit_cast<u32>(1.f));
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}
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value = get_imm(1.f);
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break;
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case OperandField::ConstFloatPos_0_5:
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value = ir.Imm32(0.5f);
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value = get_imm(0.5f);
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break;
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case OperandField::ConstFloatPos_2_0:
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value = ir.Imm32(2.0f);
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value = get_imm(2.0f);
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break;
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case OperandField::ConstFloatPos_4_0:
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value = ir.Imm32(4.0f);
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value = get_imm(4.0f);
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break;
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case OperandField::ConstFloatNeg_0_5:
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value = ir.Imm32(-0.5f);
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value = get_imm(-0.5f);
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break;
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case OperandField::ConstFloatNeg_1_0:
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if (is_float) {
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value = ir.Imm32(-1.0f);
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} else {
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value = ir.Imm32(std::bit_cast<u32>(-1.0f));
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}
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value = get_imm(-1.0f);
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break;
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case OperandField::ConstFloatNeg_2_0:
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value = ir.Imm32(-2.0f);
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value = get_imm(-2.0f);
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break;
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case OperandField::ConstFloatNeg_4_0:
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value = ir.Imm32(-4.0f);
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value = get_imm(-4.0f);
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break;
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case OperandField::VccLo:
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if (force_flt) {
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if constexpr (is_float) {
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value = ir.BitCast<IR::F32>(ir.GetVccLo());
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} else {
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value = ir.GetVccLo();
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}
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break;
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case OperandField::VccHi:
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if (force_flt) {
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if constexpr (is_float) {
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value = ir.BitCast<IR::F32>(ir.GetVccHi());
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} else {
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value = ir.GetVccHi();
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}
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break;
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case OperandField::M0:
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return m0_value;
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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return m0_value;
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}
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default:
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UNREACHABLE();
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}
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if (is_float) {
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if constexpr (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(value);
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}
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} else {
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if (operand.input_modifier.abs) {
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UNREACHABLE();
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}
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if (operand.input_modifier.neg) {
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UNREACHABLE();
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}
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}
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return value;
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}
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template IR::U32 Translator::GetSrc<IR::U32>(const InstOperand&);
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template IR::F32 Translator::GetSrc<IR::F32>(const InstOperand&);
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template <typename T>
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T Translator::GetSrc64(const InstOperand& operand) {
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constexpr bool is_float = std::is_same_v<T, IR::F64>;
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const auto get_imm = [&](auto value) -> T {
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if constexpr (is_float) {
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return ir.Imm64(std::bit_cast<double>(value));
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} else {
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return ir.Imm64(std::bit_cast<u64>(value));
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}
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};
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T value{};
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switch (operand.field) {
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case OperandField::ScalarGPR: {
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const auto value_lo = ir.GetScalarReg(IR::ScalarReg(operand.code));
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const auto value_hi = ir.GetScalarReg(IR::ScalarReg(operand.code + 1));
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(value_lo, value_hi));
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}
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break;
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}
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case OperandField::VectorGPR: {
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const auto value_lo = ir.GetVectorReg(IR::VectorReg(operand.code));
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const auto value_hi = ir.GetVectorReg(IR::VectorReg(operand.code + 1));
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(value_lo, value_hi));
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}
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break;
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}
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case OperandField::ConstZero:
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value = get_imm(0ULL);
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break;
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case OperandField::SignedConstIntPos:
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value = get_imm(s64(operand.code) - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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value = get_imm(-s64(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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value = get_imm(u64(operand.code));
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break;
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case OperandField::ConstFloatPos_1_0:
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value = get_imm(1.0);
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break;
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case OperandField::ConstFloatPos_0_5:
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value = get_imm(0.5);
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break;
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case OperandField::ConstFloatPos_2_0:
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value = get_imm(2.0);
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break;
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case OperandField::ConstFloatPos_4_0:
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value = get_imm(4.0);
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break;
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case OperandField::ConstFloatNeg_0_5:
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value = get_imm(-0.5);
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break;
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case OperandField::ConstFloatNeg_1_0:
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value = get_imm(-1.0);
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break;
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case OperandField::ConstFloatNeg_2_0:
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value = get_imm(-2.0);
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break;
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case OperandField::ConstFloatNeg_4_0:
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value = get_imm(-4.0);
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break;
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case OperandField::VccLo:
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(ir.GetVccLo(), ir.GetVccHi()));
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}
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break;
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case OperandField::VccHi:
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default:
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UNREACHABLE();
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}
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if constexpr (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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}
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@ -178,148 +267,8 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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return value;
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}
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template <>
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IR::U32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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return GetSrc<IR::U32F32>(operand, force_flt);
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}
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template <>
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IR::F32 Translator::GetSrc(const InstOperand& operand, bool) {
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return GetSrc<IR::U32F32>(operand, true);
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}
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template <>
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IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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IR::Value value_hi{};
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IR::Value value_lo{};
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bool immediate = false;
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const bool is_float = operand.type == ScalarType::Float64 || force_flt;
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (is_float) {
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value_lo = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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value_hi = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code + 1));
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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value_lo = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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value_hi = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code + 1));
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} else {
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UNREACHABLE();
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}
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break;
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case OperandField::VectorGPR:
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if (is_float) {
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value_lo = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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value_hi = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code + 1));
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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value_lo = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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value_hi = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code + 1));
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} else {
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UNREACHABLE();
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}
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break;
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case OperandField::ConstZero:
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immediate = true;
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if (force_flt) {
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value_lo = ir.Imm64(0.0);
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} else {
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value_lo = ir.Imm64(u64(0U));
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}
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break;
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case OperandField::SignedConstIntPos:
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ASSERT(!force_flt);
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immediate = true;
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value_lo = ir.Imm64(s64(operand.code) - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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ASSERT(!force_flt);
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immediate = true;
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value_lo = ir.Imm64(-s64(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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immediate = true;
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if (force_flt) {
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UNREACHABLE(); // There is a literal double?
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} else {
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value_lo = ir.Imm64(u64(operand.code));
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}
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break;
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case OperandField::ConstFloatPos_1_0:
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immediate = true;
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if (force_flt) {
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value_lo = ir.Imm64(1.0);
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} else {
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value_lo = ir.Imm64(std::bit_cast<u64>(f64(1.0)));
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}
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break;
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case OperandField::ConstFloatPos_0_5:
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immediate = true;
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value_lo = ir.Imm64(0.5);
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break;
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case OperandField::ConstFloatPos_2_0:
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immediate = true;
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value_lo = ir.Imm64(2.0);
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break;
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case OperandField::ConstFloatPos_4_0:
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immediate = true;
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value_lo = ir.Imm64(4.0);
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break;
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case OperandField::ConstFloatNeg_0_5:
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immediate = true;
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value_lo = ir.Imm64(-0.5);
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break;
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case OperandField::ConstFloatNeg_1_0:
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immediate = true;
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value_lo = ir.Imm64(-1.0);
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break;
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case OperandField::ConstFloatNeg_2_0:
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immediate = true;
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value_lo = ir.Imm64(-2.0);
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break;
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case OperandField::ConstFloatNeg_4_0:
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immediate = true;
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value_lo = ir.Imm64(-4.0);
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break;
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case OperandField::VccLo: {
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value_lo = ir.GetVccLo();
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value_hi = ir.GetVccHi();
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} break;
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case OperandField::VccHi:
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UNREACHABLE();
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default:
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UNREACHABLE();
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}
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IR::Value value;
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if (immediate) {
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value = value_lo;
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} else if (is_float) {
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throw NotImplementedException("required OpPackDouble2x32 implementation");
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} else {
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IR::Value packed = ir.CompositeConstruct(value_lo, value_hi);
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value = ir.PackUint2x32(packed);
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}
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if (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(IR::F32F64(value));
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(IR::F32F64(value));
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}
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}
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return IR::U64F64(value);
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}
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template <>
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IR::U64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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return GetSrc64<IR::U64F64>(operand, force_flt);
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}
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template <>
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IR::F64 Translator::GetSrc64(const InstOperand& operand, bool) {
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return GetSrc64<IR::U64F64>(operand, true);
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}
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template IR::U64 Translator::GetSrc64<IR::U64>(const InstOperand&);
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template IR::F64 Translator::GetSrc64<IR::F64>(const InstOperand&);
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void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
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IR::U32F32 result = value;
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@ -211,10 +211,10 @@ public:
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void IMAGE_ATOMIC(AtomicOp op, const GcnInst& inst);
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private:
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template <typename T = IR::U32F32>
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[[nodiscard]] T GetSrc(const InstOperand& operand, bool flt_zero = false);
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template <typename T = IR::U64F64>
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[[nodiscard]] T GetSrc64(const InstOperand& operand, bool flt_zero = false);
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template <typename T = IR::U32>
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[[nodiscard]] T GetSrc(const InstOperand& operand);
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template <typename T = IR::U64>
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[[nodiscard]] T GetSrc64(const InstOperand& operand);
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void SetDst(const InstOperand& operand, const IR::U32F32& value);
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void SetDst64(const InstOperand& operand, const IR::U64F64& value_raw);
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@ -2,7 +2,6 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/profile.h"
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namespace Shader::Gcn {
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@ -312,7 +311,7 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
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}
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void Translator::V_MOV(const GcnInst& inst) {
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SetDst(inst.dst[0], GetSrc(inst.src[0]));
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SetDst(inst.dst[0], GetSrc<IR::F32>(inst.src[0]));
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}
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void Translator::V_SAD(const GcnInst& inst) {
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@ -321,14 +320,14 @@ void Translator::V_SAD(const GcnInst& inst) {
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}
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void Translator::V_MAC_F32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.FPFma(GetSrc(inst.src[0], true), GetSrc(inst.src[1], true),
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GetSrc(inst.dst[0], true)));
|
||||
SetDst(inst.dst[0], ir.FPFma(GetSrc<IR::F32>(inst.src[0]), GetSrc<IR::F32>(inst.src[1]),
|
||||
GetSrc<IR::F32>(inst.dst[0])));
|
||||
}
|
||||
|
||||
void Translator::V_CVT_PKRTZ_F16_F32(const GcnInst& inst) {
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
const IR::Value vec_f32 =
|
||||
ir.CompositeConstruct(GetSrc(inst.src[0], true), GetSrc(inst.src[1], true));
|
||||
ir.CompositeConstruct(GetSrc<IR::F32>(inst.src[0]), GetSrc<IR::F32>(inst.src[1]));
|
||||
ir.SetVectorReg(dst_reg, ir.PackHalf2x16(vec_f32));
|
||||
}
|
||||
|
||||
|
|
@ -339,13 +338,13 @@ void Translator::V_CVT_F32_F16(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_CVT_F16_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0 = GetSrc(inst.src[0], true);
|
||||
const IR::F32 src0 = GetSrc<IR::F32>(inst.src[0]);
|
||||
const IR::F16 src0fp16 = ir.FPConvert(16, src0);
|
||||
SetDst(inst.dst[0], ir.UConvert(32, ir.BitCast<IR::U16>(src0fp16)));
|
||||
}
|
||||
|
||||
void Translator::V_MUL_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], ir.FPMul(GetSrc(inst.src[0], true), GetSrc(inst.src[1], true)));
|
||||
SetDst(inst.dst[0], ir.FPMul(GetSrc<IR::F32>(inst.src[0]), GetSrc<IR::F32>(inst.src[1])));
|
||||
}
|
||||
|
||||
void Translator::V_CNDMASK_B32(const GcnInst& inst) {
|
||||
|
|
@ -354,24 +353,8 @@ void Translator::V_CNDMASK_B32(const GcnInst& inst) {
|
|||
const IR::U1 flag = inst.src[2].field == OperandField::ScalarGPR
|
||||
? ir.GetThreadBitScalarReg(flag_reg)
|
||||
: ir.GetVcc();
|
||||
|
||||
// We can treat the instruction as integer most of the time, but when a source is
|
||||
// a floating point constant we will force the other as float for better readability
|
||||
// The other operand is also higly likely to be float as well.
|
||||
const auto is_float_const = [](OperandField field) {
|
||||
return field >= OperandField::ConstFloatPos_0_5 && field <= OperandField::ConstFloatNeg_4_0;
|
||||
};
|
||||
const bool has_flt_source =
|
||||
is_float_const(inst.src[0].field) || is_float_const(inst.src[1].field);
|
||||
IR::U32F32 src0 = GetSrc(inst.src[0], has_flt_source);
|
||||
IR::U32F32 src1 = GetSrc(inst.src[1], has_flt_source);
|
||||
if (src0.Type() == IR::Type::F32 && src1.Type() == IR::Type::U32) {
|
||||
src1 = ir.BitCast<IR::F32, IR::U32>(src1);
|
||||
}
|
||||
if (src1.Type() == IR::Type::F32 && src0.Type() == IR::Type::U32) {
|
||||
src0 = ir.BitCast<IR::F32, IR::U32>(src0);
|
||||
}
|
||||
const IR::Value result = ir.Select(flag, src1, src0);
|
||||
const IR::Value result =
|
||||
ir.Select(flag, GetSrc<IR::F32>(inst.src[1]), GetSrc<IR::F32>(inst.src[0]));
|
||||
ir.SetVectorReg(dst_reg, IR::U32F32{result});
|
||||
}
|
||||
|
||||
|
|
@ -448,21 +431,21 @@ void Translator::V_CVT_F32_U32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_MAD_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 src2{GetSrc(inst.src[2], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
const IR::F32 src2{GetSrc<IR::F32>(inst.src[2])};
|
||||
SetDst(inst.dst[0], ir.FPFma(src0, src1, src2));
|
||||
}
|
||||
|
||||
void Translator::V_FRACT_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
ir.SetVectorReg(dst_reg, ir.Fract(src0));
|
||||
}
|
||||
|
||||
void Translator::V_ADD_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.FPAdd(src0, src1));
|
||||
}
|
||||
|
||||
|
|
@ -476,9 +459,9 @@ void Translator::V_CVT_OFF_F32_I4(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_MED3_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 src2{GetSrc(inst.src[2], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
const IR::F32 src2{GetSrc<IR::F32>(inst.src[2])};
|
||||
const IR::F32 mmx = ir.FPMin(ir.FPMax(src0, src1), src2);
|
||||
SetDst(inst.dst[0], ir.FPMax(ir.FPMin(src0, src1), mmx));
|
||||
}
|
||||
|
|
@ -492,32 +475,32 @@ void Translator::V_MED3_I32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_FLOOR_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
ir.SetVectorReg(dst_reg, ir.FPFloor(src0));
|
||||
}
|
||||
|
||||
void Translator::V_SUB_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.FPSub(src0, src1));
|
||||
}
|
||||
|
||||
void Translator::V_RCP_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.FPRecip(src0));
|
||||
}
|
||||
|
||||
void Translator::V_FMA_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 src2{GetSrc(inst.src[2], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
const IR::F32 src2{GetSrc<IR::F32>(inst.src[2])};
|
||||
SetDst(inst.dst[0], ir.FPFma(src0, src1, src2));
|
||||
}
|
||||
|
||||
void Translator::V_CMP_F32(ConditionOp op, bool set_exec, const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
const IR::U1 result = [&] {
|
||||
switch (op) {
|
||||
case ConditionOp::F:
|
||||
|
|
@ -557,8 +540,8 @@ void Translator::V_CMP_F32(ConditionOp op, bool set_exec, const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_MAX_F32(const GcnInst& inst, bool is_legacy) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.FPMax(src0, src1, is_legacy));
|
||||
}
|
||||
|
||||
|
|
@ -569,40 +552,40 @@ void Translator::V_MAX_U32(bool is_signed, const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_RSQ_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.FPRecipSqrt(src0));
|
||||
}
|
||||
|
||||
void Translator::V_SIN_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.FPSin(src0));
|
||||
}
|
||||
|
||||
void Translator::V_LOG_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.FPLog2(src0));
|
||||
}
|
||||
|
||||
void Translator::V_EXP_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.FPExp2(src0));
|
||||
}
|
||||
|
||||
void Translator::V_SQRT_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.FPSqrt(src0));
|
||||
}
|
||||
|
||||
void Translator::V_MIN_F32(const GcnInst& inst, bool is_legacy) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.FPMin(src0, src1, is_legacy));
|
||||
}
|
||||
|
||||
void Translator::V_MIN3_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 src2{GetSrc(inst.src[2], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
const IR::F32 src2{GetSrc<IR::F32>(inst.src[2])};
|
||||
SetDst(inst.dst[0], ir.FPMin(src0, ir.FPMin(src1, src2)));
|
||||
}
|
||||
|
||||
|
|
@ -614,9 +597,9 @@ void Translator::V_MIN3_I32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_MADMK_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 k{GetSrc(inst.src[2], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
const IR::F32 k{GetSrc<IR::F32>(inst.src[2])};
|
||||
SetDst(inst.dst[0], ir.FPFma(src0, k, src1));
|
||||
}
|
||||
|
||||
|
|
@ -625,25 +608,25 @@ void Translator::V_CUBEMA_F32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_CUBESC_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], GetSrc(inst.src[0], true));
|
||||
SetDst(inst.dst[0], GetSrc<IR::F32>(inst.src[0]));
|
||||
}
|
||||
|
||||
void Translator::V_CUBETC_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], GetSrc(inst.src[1], true));
|
||||
SetDst(inst.dst[0], GetSrc<IR::F32>(inst.src[1]));
|
||||
}
|
||||
|
||||
void Translator::V_CUBEID_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], GetSrc(inst.src[2], true));
|
||||
SetDst(inst.dst[0], GetSrc<IR::F32>(inst.src[2]));
|
||||
}
|
||||
|
||||
void Translator::V_CVT_U32_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.ConvertFToU(32, src0));
|
||||
}
|
||||
|
||||
void Translator::V_SUBREV_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.FPSub(src1, src0));
|
||||
}
|
||||
|
||||
|
|
@ -727,9 +710,17 @@ void Translator::V_SAD_U32(const GcnInst& inst) {
|
|||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::U32 src2{GetSrc(inst.src[2])};
|
||||
const IR::U32 max{ir.IMax(src0, src1, false)};
|
||||
const IR::U32 min{ir.IMin(src0, src1, false)};
|
||||
SetDst(inst.dst[0], ir.IAdd(ir.ISub(max, min), src2));
|
||||
IR::U32 result;
|
||||
if (src0.IsImmediate() && src0.U32() == 0U) {
|
||||
result = src1;
|
||||
} else if (src1.IsImmediate() && src1.U32() == 0U) {
|
||||
result = src0;
|
||||
} else {
|
||||
const IR::U32 max{ir.IMax(src0, src1, false)};
|
||||
const IR::U32 min{ir.IMin(src0, src1, false)};
|
||||
result = ir.ISub(max, min);
|
||||
}
|
||||
SetDst(inst.dst[0], ir.IAdd(result, src2));
|
||||
}
|
||||
|
||||
void Translator::V_BFE_U32(bool is_signed, const GcnInst& inst) {
|
||||
|
|
@ -783,7 +774,7 @@ void Translator::V_MAD_U32_U24(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_RNDNE_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.FPRoundEven(src0));
|
||||
}
|
||||
|
||||
|
|
@ -794,14 +785,14 @@ void Translator::V_BCNT_U32_B32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_COS_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.FPCos(src0));
|
||||
}
|
||||
|
||||
void Translator::V_MAX3_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::F32 src2{GetSrc(inst.src[2], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};
|
||||
const IR::F32 src2{GetSrc<IR::F32>(inst.src[2])};
|
||||
SetDst(inst.dst[0], ir.FPMax(src0, ir.FPMax(src1, src2)));
|
||||
}
|
||||
|
||||
|
|
@ -813,7 +804,7 @@ void Translator::V_MAX3_U32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_CVT_I32_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.ConvertFToS(32, src0));
|
||||
}
|
||||
|
||||
|
|
@ -830,12 +821,12 @@ void Translator::V_MUL_LO_U32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_TRUNC_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.FPTrunc(src0));
|
||||
}
|
||||
|
||||
void Translator::V_CEIL_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.FPCeil(src0));
|
||||
}
|
||||
|
||||
|
|
@ -899,18 +890,18 @@ void Translator::V_BFREV_B32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_LDEXP_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.FPLdexp(src0, src1));
|
||||
}
|
||||
|
||||
void Translator::V_CVT_FLR_I32_F32(const GcnInst& inst) {
|
||||
const IR::F32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.ConvertFToI(32, true, ir.FPFloor(src0)));
|
||||
}
|
||||
|
||||
void Translator::V_CMP_CLASS_F32(const GcnInst& inst) {
|
||||
const IR::F32F64 src0{GetSrc(inst.src[0])};
|
||||
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
IR::U1 value;
|
||||
if (src1.IsImmediate()) {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue