mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-07-02 07:16:16 +00:00
video_core: Crucial buffer cache fixes + proper GPU clears (#414)
* translator: Use templates for stronger type guarantees * spirv: Define buffer offsets upfront * Saves a lot of shader instructions * buffer_cache: Use dynamic vertex input when available * Fixes issues when games like dark souls rebind vertex buffers with different stride * externals: Update boost * spirv: Use runtime array for ssbos * ssbos can be large and typically their size will vary, especially in generic copy/clear cs shaders * fs: Lock when doing case insensitive search * Dark Souls does fs lookups from different threads * texture_cache: More precise invalidation from compute * Fixes unrelated render targets being cleared * texture_cache: Use hashes for protect gpu modified images from reupload * translator: Treat V_CNDMASK as float * Sometimes it can have input modifiers. Worst this will cause is some extra calls to uintBitsToFloat and opposite. But most often this is used as float anyway * translator: Small optimization for V_SAD_U32 * Fix review * clang format
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23 changed files with 372 additions and 346 deletions
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@ -73,101 +73,190 @@ void Translator::EmitPrologue() {
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}
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}
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template <>
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IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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IR::U32F32 value{};
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template <typename T>
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T Translator::GetSrc(const InstOperand& operand) {
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constexpr bool is_float = std::is_same_v<T, IR::F32>;
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const bool is_float = operand.type == ScalarType::Float32 || force_flt;
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const auto get_imm = [&](auto value) -> T {
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if constexpr (is_float) {
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return ir.Imm32(std::bit_cast<float>(value));
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} else {
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return ir.Imm32(std::bit_cast<u32>(value));
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}
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};
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T value{};
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (is_float) {
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value = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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} else {
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value = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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}
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value = ir.GetScalarReg<T>(IR::ScalarReg(operand.code));
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break;
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case OperandField::VectorGPR:
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if (is_float) {
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value = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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} else {
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value = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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}
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value = ir.GetVectorReg<T>(IR::VectorReg(operand.code));
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break;
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case OperandField::ConstZero:
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if (is_float) {
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value = ir.Imm32(0.f);
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} else {
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value = ir.Imm32(0U);
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}
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value = get_imm(0U);
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break;
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case OperandField::SignedConstIntPos:
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ASSERT(!force_flt);
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value = ir.Imm32(operand.code - SignedConstIntPosMin + 1);
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value = get_imm(operand.code - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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ASSERT(!force_flt);
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value = ir.Imm32(-s32(operand.code) + SignedConstIntNegMin - 1);
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value = get_imm(-s32(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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if (is_float) {
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value = ir.Imm32(std::bit_cast<float>(operand.code));
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} else {
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value = ir.Imm32(operand.code);
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}
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value = get_imm(operand.code);
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break;
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case OperandField::ConstFloatPos_1_0:
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if (is_float) {
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value = ir.Imm32(1.f);
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} else {
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value = ir.Imm32(std::bit_cast<u32>(1.f));
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}
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value = get_imm(1.f);
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break;
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case OperandField::ConstFloatPos_0_5:
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value = ir.Imm32(0.5f);
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value = get_imm(0.5f);
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break;
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case OperandField::ConstFloatPos_2_0:
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value = ir.Imm32(2.0f);
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value = get_imm(2.0f);
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break;
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case OperandField::ConstFloatPos_4_0:
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value = ir.Imm32(4.0f);
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value = get_imm(4.0f);
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break;
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case OperandField::ConstFloatNeg_0_5:
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value = ir.Imm32(-0.5f);
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value = get_imm(-0.5f);
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break;
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case OperandField::ConstFloatNeg_1_0:
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if (is_float) {
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value = ir.Imm32(-1.0f);
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} else {
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value = ir.Imm32(std::bit_cast<u32>(-1.0f));
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}
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value = get_imm(-1.0f);
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break;
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case OperandField::ConstFloatNeg_2_0:
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value = ir.Imm32(-2.0f);
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value = get_imm(-2.0f);
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break;
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case OperandField::ConstFloatNeg_4_0:
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value = ir.Imm32(-4.0f);
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value = get_imm(-4.0f);
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break;
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case OperandField::VccLo:
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if (force_flt) {
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if constexpr (is_float) {
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value = ir.BitCast<IR::F32>(ir.GetVccLo());
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} else {
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value = ir.GetVccLo();
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}
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break;
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case OperandField::VccHi:
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if (force_flt) {
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if constexpr (is_float) {
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value = ir.BitCast<IR::F32>(ir.GetVccHi());
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} else {
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value = ir.GetVccHi();
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}
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break;
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case OperandField::M0:
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return m0_value;
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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return m0_value;
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}
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default:
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UNREACHABLE();
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}
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if (is_float) {
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if constexpr (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(value);
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}
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} else {
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if (operand.input_modifier.abs) {
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UNREACHABLE();
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}
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if (operand.input_modifier.neg) {
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UNREACHABLE();
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}
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}
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return value;
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}
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template IR::U32 Translator::GetSrc<IR::U32>(const InstOperand&);
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template IR::F32 Translator::GetSrc<IR::F32>(const InstOperand&);
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template <typename T>
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T Translator::GetSrc64(const InstOperand& operand) {
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constexpr bool is_float = std::is_same_v<T, IR::F64>;
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const auto get_imm = [&](auto value) -> T {
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if constexpr (is_float) {
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return ir.Imm64(std::bit_cast<double>(value));
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} else {
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return ir.Imm64(std::bit_cast<u64>(value));
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}
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};
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T value{};
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switch (operand.field) {
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case OperandField::ScalarGPR: {
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const auto value_lo = ir.GetScalarReg(IR::ScalarReg(operand.code));
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const auto value_hi = ir.GetScalarReg(IR::ScalarReg(operand.code + 1));
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(value_lo, value_hi));
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}
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break;
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}
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case OperandField::VectorGPR: {
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const auto value_lo = ir.GetVectorReg(IR::VectorReg(operand.code));
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const auto value_hi = ir.GetVectorReg(IR::VectorReg(operand.code + 1));
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(value_lo, value_hi));
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}
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break;
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}
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case OperandField::ConstZero:
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value = get_imm(0ULL);
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break;
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case OperandField::SignedConstIntPos:
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value = get_imm(s64(operand.code) - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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value = get_imm(-s64(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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value = get_imm(u64(operand.code));
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break;
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case OperandField::ConstFloatPos_1_0:
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value = get_imm(1.0);
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break;
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case OperandField::ConstFloatPos_0_5:
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value = get_imm(0.5);
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break;
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case OperandField::ConstFloatPos_2_0:
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value = get_imm(2.0);
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break;
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case OperandField::ConstFloatPos_4_0:
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value = get_imm(4.0);
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break;
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case OperandField::ConstFloatNeg_0_5:
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value = get_imm(-0.5);
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break;
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case OperandField::ConstFloatNeg_1_0:
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value = get_imm(-1.0);
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break;
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case OperandField::ConstFloatNeg_2_0:
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value = get_imm(-2.0);
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break;
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case OperandField::ConstFloatNeg_4_0:
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value = get_imm(-4.0);
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break;
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case OperandField::VccLo:
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if constexpr (is_float) {
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UNREACHABLE();
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} else {
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value = ir.PackUint2x32(ir.CompositeConstruct(ir.GetVccLo(), ir.GetVccHi()));
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}
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break;
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case OperandField::VccHi:
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default:
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UNREACHABLE();
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}
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if constexpr (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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}
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@ -178,148 +267,8 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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return value;
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}
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template <>
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IR::U32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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return GetSrc<IR::U32F32>(operand, force_flt);
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}
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template <>
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IR::F32 Translator::GetSrc(const InstOperand& operand, bool) {
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return GetSrc<IR::U32F32>(operand, true);
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}
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template <>
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IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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IR::Value value_hi{};
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IR::Value value_lo{};
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bool immediate = false;
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const bool is_float = operand.type == ScalarType::Float64 || force_flt;
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (is_float) {
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value_lo = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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value_hi = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code + 1));
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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value_lo = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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value_hi = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code + 1));
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} else {
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UNREACHABLE();
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}
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break;
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case OperandField::VectorGPR:
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if (is_float) {
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value_lo = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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value_hi = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code + 1));
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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value_lo = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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value_hi = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code + 1));
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} else {
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UNREACHABLE();
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}
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break;
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case OperandField::ConstZero:
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immediate = true;
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if (force_flt) {
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value_lo = ir.Imm64(0.0);
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} else {
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value_lo = ir.Imm64(u64(0U));
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}
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break;
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case OperandField::SignedConstIntPos:
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ASSERT(!force_flt);
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immediate = true;
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value_lo = ir.Imm64(s64(operand.code) - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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ASSERT(!force_flt);
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immediate = true;
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value_lo = ir.Imm64(-s64(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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immediate = true;
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if (force_flt) {
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UNREACHABLE(); // There is a literal double?
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} else {
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value_lo = ir.Imm64(u64(operand.code));
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}
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break;
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case OperandField::ConstFloatPos_1_0:
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immediate = true;
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if (force_flt) {
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value_lo = ir.Imm64(1.0);
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} else {
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value_lo = ir.Imm64(std::bit_cast<u64>(f64(1.0)));
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}
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break;
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case OperandField::ConstFloatPos_0_5:
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immediate = true;
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value_lo = ir.Imm64(0.5);
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break;
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case OperandField::ConstFloatPos_2_0:
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immediate = true;
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value_lo = ir.Imm64(2.0);
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break;
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case OperandField::ConstFloatPos_4_0:
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immediate = true;
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value_lo = ir.Imm64(4.0);
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break;
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case OperandField::ConstFloatNeg_0_5:
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immediate = true;
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value_lo = ir.Imm64(-0.5);
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break;
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case OperandField::ConstFloatNeg_1_0:
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immediate = true;
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value_lo = ir.Imm64(-1.0);
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break;
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case OperandField::ConstFloatNeg_2_0:
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immediate = true;
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value_lo = ir.Imm64(-2.0);
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break;
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case OperandField::ConstFloatNeg_4_0:
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immediate = true;
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value_lo = ir.Imm64(-4.0);
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break;
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case OperandField::VccLo: {
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value_lo = ir.GetVccLo();
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value_hi = ir.GetVccHi();
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} break;
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case OperandField::VccHi:
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UNREACHABLE();
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default:
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UNREACHABLE();
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}
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IR::Value value;
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if (immediate) {
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value = value_lo;
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} else if (is_float) {
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throw NotImplementedException("required OpPackDouble2x32 implementation");
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} else {
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IR::Value packed = ir.CompositeConstruct(value_lo, value_hi);
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value = ir.PackUint2x32(packed);
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}
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if (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(IR::F32F64(value));
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(IR::F32F64(value));
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}
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}
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return IR::U64F64(value);
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}
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template <>
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IR::U64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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return GetSrc64<IR::U64F64>(operand, force_flt);
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}
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template <>
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IR::F64 Translator::GetSrc64(const InstOperand& operand, bool) {
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return GetSrc64<IR::U64F64>(operand, true);
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}
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template IR::U64 Translator::GetSrc64<IR::U64>(const InstOperand&);
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template IR::F64 Translator::GetSrc64<IR::F64>(const InstOperand&);
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void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
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IR::U32F32 result = value;
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