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https://github.com/shadps4-emu/shadPS4.git
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Handle R128 bit in MIMG instructions (#3010)
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parent
8fffdc3918
commit
2091bc5651
5 changed files with 15 additions and 2 deletions
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@ -1032,7 +1032,6 @@ void GcnDecodeContext::decodeInstructionMIMG(uint64_t hexInstruction) {
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m_instruction.control.mimg = *reinterpret_cast<InstControlMIMG*>(&hexInstruction);
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m_instruction.control.mimg.mod = getMimgModifier(m_instruction.opcode);
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ASSERT(m_instruction.control.mimg.r128 == 0);
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}
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void GcnDecodeContext::decodeInstructionDS(uint64_t hexInstruction) {
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@ -377,6 +377,7 @@ void Translator::IMAGE_LOAD(bool has_mip, const GcnInst& inst) {
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IR::TextureInstInfo info{};
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info.has_lod.Assign(has_mip);
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info.is_array.Assign(mimg.da);
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info.is_r128.Assign(mimg.r128);
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const IR::Value texel = ir.ImageRead(handle, body, {}, {}, info);
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for (u32 i = 0; i < 4; i++) {
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@ -426,6 +427,7 @@ void Translator::IMAGE_GET_RESINFO(const GcnInst& inst) {
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IR::TextureInstInfo info{};
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info.is_array.Assign(mimg.da);
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info.is_r128.Assign(mimg.r128);
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const IR::Value size = ir.ImageQueryDimension(tsharp, lod, ir.Imm1(has_mips), info);
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@ -451,6 +453,7 @@ void Translator::IMAGE_ATOMIC(AtomicOp op, const GcnInst& inst) {
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IR::TextureInstInfo info{};
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info.is_array.Assign(mimg.da);
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info.is_r128.Assign(mimg.r128);
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const IR::Value value = ir.GetVectorReg(val_reg);
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const IR::Value handle = ir.GetScalarReg(tsharp_reg);
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@ -509,6 +512,7 @@ IR::Value EmitImageSample(IR::IREmitter& ir, const GcnInst& inst, const IR::Scal
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info.has_lod.Assign(flags.any(MimgModifier::Lod));
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info.is_array.Assign(mimg.da);
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info.is_unnormalized.Assign(mimg.unrm);
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info.is_r128.Assign(mimg.r128);
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if (gather) {
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info.gather_comp.Assign(std::bit_width(mimg.dmask) - 1);
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@ -617,6 +621,7 @@ void Translator::IMAGE_GET_LOD(const GcnInst& inst) {
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IR::TextureInstInfo info{};
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info.is_array.Assign(mimg.da);
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info.is_r128.Assign(mimg.r128);
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const IR::Value handle = ir.GetScalarReg(tsharp_reg);
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const IR::Value body = ir.CompositeConstruct(
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@ -84,6 +84,7 @@ struct ImageResource {
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bool is_atomic{};
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bool is_array{};
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bool is_written{};
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bool is_r128{};
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[[nodiscard]] constexpr AmdGpu::Image GetSharp(const Info& info) const noexcept;
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};
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@ -293,7 +294,13 @@ constexpr AmdGpu::Buffer BufferResource::GetSharp(const Info& info) const noexce
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}
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constexpr AmdGpu::Image ImageResource::GetSharp(const Info& info) const noexcept {
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const auto image = info.ReadUdSharp<AmdGpu::Image>(sharp_idx);
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AmdGpu::Image image{0};
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if (!is_r128) {
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image = info.ReadUdSharp<AmdGpu::Image>(sharp_idx);
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} else {
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AmdGpu::Buffer buf = info.ReadUdSharp<AmdGpu::Buffer>(sharp_idx);
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memcpy(&image, &buf, sizeof(buf));
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}
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if (!image.Valid()) {
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// Fall back to null image if unbound.
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return AmdGpu::Image::Null();
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@ -411,6 +411,7 @@ void PatchImageSharp(IR::Block& block, IR::Inst& inst, Info& info, Descriptors&
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.is_atomic = IsImageAtomicInstruction(inst),
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.is_array = bool(inst_info.is_array),
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.is_written = is_written,
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.is_r128 = bool(inst_info.is_r128),
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});
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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@ -44,6 +44,7 @@ union TextureInstInfo {
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BitField<9, 1, u32> is_array;
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BitField<10, 1, u32> is_unnormalized;
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BitField<11, 1, u32> is_gather;
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BitField<12, 1, u32> is_r128;
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};
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union BufferInstInfo {
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