Handle DS_READ_U16, DS_WRITE_B16, DS_ADD_U64 (#3007)

* Handle DS_READ_U16 & DS_WRITE_B16

* Refactor DS translation

* Translate DS_ADD_U64

* format

* Fix RingAccessElimination after changing WriteShared64 type

* Simplify bounds checking in generated SPIR-V

src/shader_recompiler/backend/spirv/emit_spirv.cpp

@@ -303,6 +303,11 @@ void SetupCapabilities(const Info& info, const Profile& profile, EmitContext& ct
         ctx.AddCapability(spv::Capability::PhysicalStorageBufferAddresses);
         ctx.AddExtension("SPV_KHR_physical_storage_buffer");
     }
+    if (info.uses_shared && profile.supports_workgroup_explicit_memory_layout) {
+        ctx.AddExtension("SPV_KHR_workgroup_memory_explicit_layout");
+        ctx.AddCapability(spv::Capability::WorkgroupMemoryExplicitLayoutKHR);
+        ctx.AddCapability(spv::Capability::WorkgroupMemoryExplicitLayout16BitAccessKHR);
+    }
 }
 
 void DefineEntryPoint(const Info& info, EmitContext& ctx, Id main) {

src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp

@@ -1,6 +1,8 @@
 // SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 
+#include "common/div_ceil.h"
+#include "shader_recompiler/backend/spirv/emit_spirv_bounds.h"
 #include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
 #include "shader_recompiler/backend/spirv/spirv_emit_context.h"
 
@@ -15,42 +17,40 @@ std::pair<Id, Id> AtomicArgs(EmitContext& ctx) {
 Id SharedAtomicU32(EmitContext& ctx, Id offset, Id value,
                    Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
     const Id shift_id{ctx.ConstU32(2U)};
-    const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
-    const Id pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, index)};
+    const Id index{ctx.OpShiftRightLogical(ctx.U32[1], offset, shift_id)};
+    const u32 num_elements{Common::DivCeil(ctx.runtime_info.cs_info.shared_memory_size, 4u)};
+    const Id pointer{
+        ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, ctx.u32_zero_value, index)};
     const auto [scope, semantics]{AtomicArgs(ctx)};
-    return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics, value);
+    return AccessBoundsCheck<32>(ctx, index, ctx.ConstU32(num_elements), [&] {
+        return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics, value);
+    });
+}
+
+Id SharedAtomicU64(EmitContext& ctx, Id offset, Id value,
+                   Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
+    const Id shift_id{ctx.ConstU32(3U)};
+    const Id index{ctx.OpShiftRightLogical(ctx.U32[1], offset, shift_id)};
+    const u32 num_elements{Common::DivCeil(ctx.runtime_info.cs_info.shared_memory_size, 8u)};
+    const Id pointer{
+        ctx.OpAccessChain(ctx.shared_u64, ctx.shared_memory_u64, ctx.u32_zero_value, index)};
+    const auto [scope, semantics]{AtomicArgs(ctx)};
+    return AccessBoundsCheck<64>(ctx, index, ctx.ConstU32(num_elements), [&] {
+        return (ctx.*atomic_func)(ctx.U64, pointer, scope, semantics, value);
+    });
 }
 
 Id SharedAtomicU32_IncDec(EmitContext& ctx, Id offset,
                           Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id)) {
     const Id shift_id{ctx.ConstU32(2U)};
-    const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
-    const Id pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, index)};
+    const Id index{ctx.OpShiftRightLogical(ctx.U32[1], offset, shift_id)};
+    const u32 num_elements{Common::DivCeil(ctx.runtime_info.cs_info.shared_memory_size, 4u)};
+    const Id pointer{
+        ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, ctx.u32_zero_value, index)};
     const auto [scope, semantics]{AtomicArgs(ctx)};
-    return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics);
-}
-
-Id BufferAtomicU32BoundsCheck(EmitContext& ctx, Id index, Id buffer_size, auto emit_func) {
-    if (Sirit::ValidId(buffer_size)) {
-        // Bounds checking enabled, wrap in a conditional branch to make sure that
-        // the atomic is not mistakenly executed when the index is out of bounds.
-        const Id in_bounds = ctx.OpULessThan(ctx.U1[1], index, buffer_size);
-        const Id ib_label = ctx.OpLabel();
-        const Id oob_label = ctx.OpLabel();
-        const Id end_label = ctx.OpLabel();
-        ctx.OpSelectionMerge(end_label, spv::SelectionControlMask::MaskNone);
-        ctx.OpBranchConditional(in_bounds, ib_label, oob_label);
-        ctx.AddLabel(ib_label);
-        const Id ib_result = emit_func();
-        ctx.OpBranch(end_label);
-        ctx.AddLabel(oob_label);
-        const Id oob_result = ctx.u32_zero_value;
-        ctx.OpBranch(end_label);
-        ctx.AddLabel(end_label);
-        return ctx.OpPhi(ctx.U32[1], ib_result, ib_label, oob_result, oob_label);
-    }
-    // Bounds checking not enabled, just perform the atomic operation.
-    return emit_func();
+    return AccessBoundsCheck<32>(ctx, index, ctx.ConstU32(num_elements), [&] {
+        return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics);
+    });
 }
 
 Id BufferAtomicU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value,
@@ -63,7 +63,7 @@ Id BufferAtomicU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id
     const auto [id, pointer_type] = buffer[EmitContext::PointerType::U32];
     const Id ptr = ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index);
     const auto [scope, semantics]{AtomicArgs(ctx)};
-    return BufferAtomicU32BoundsCheck(ctx, index, buffer.size_dwords, [&] {
+    return AccessBoundsCheck<32>(ctx, index, buffer.size_dwords, [&] {
         return (ctx.*atomic_func)(ctx.U32[1], ptr, scope, semantics, value);
     });
 }
@@ -79,11 +79,26 @@ Id BufferAtomicU32CmpSwap(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addre
     const auto [id, pointer_type] = buffer[EmitContext::PointerType::U32];
     const Id ptr = ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index);
     const auto [scope, semantics]{AtomicArgs(ctx)};
-    return BufferAtomicU32BoundsCheck(ctx, index, buffer.size_dwords, [&] {
+    return AccessBoundsCheck<32>(ctx, index, buffer.size_dwords, [&] {
         return (ctx.*atomic_func)(ctx.U32[1], ptr, scope, semantics, semantics, value, cmp_value);
     });
 }
 
+Id BufferAtomicU64(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value,
+                   Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
+    const auto& buffer = ctx.buffers[handle];
+    if (Sirit::ValidId(buffer.offset)) {
+        address = ctx.OpIAdd(ctx.U32[1], address, buffer.offset);
+    }
+    const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(3u));
+    const auto [id, pointer_type] = buffer[EmitContext::PointerType::U64];
+    const Id ptr = ctx.OpAccessChain(pointer_type, id, ctx.u32_zero_value, index);
+    const auto [scope, semantics]{AtomicArgs(ctx)};
+    return AccessBoundsCheck<64>(ctx, index, buffer.size_qwords, [&] {
+        return (ctx.*atomic_func)(ctx.U64, ptr, scope, semantics, value);
+    });
+}
+
 Id ImageAtomicU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id value,
                   Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
     const auto& texture = ctx.images[handle & 0xFFFF];
@@ -105,6 +120,10 @@ Id EmitSharedAtomicIAdd32(EmitContext& ctx, Id offset, Id value) {
     return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicIAdd);
 }
 
+Id EmitSharedAtomicIAdd64(EmitContext& ctx, Id offset, Id value) {
+    return SharedAtomicU64(ctx, offset, value, &Sirit::Module::OpAtomicIAdd);
+}
+
 Id EmitSharedAtomicUMax32(EmitContext& ctx, Id offset, Id value) {
     return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicUMax);
 }
@@ -149,6 +168,10 @@ Id EmitBufferAtomicIAdd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addre
     return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicIAdd);
 }
 
+Id EmitBufferAtomicIAdd64(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
+    return BufferAtomicU64(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicIAdd);
+}
+
 Id EmitBufferAtomicSMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
     return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicSMin);
 }

src/shader_recompiler/backend/spirv/emit_spirv_bounds.h

@@ -0,0 +1,48 @@
+// SPDX-FileCopyrightText: Copyright 2025 shadPS4 Emulator Project
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
+#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
+
+namespace Shader::Backend::SPIRV {
+
+template <u32 bit_size>
+auto AccessBoundsCheck(EmitContext& ctx, Id index, Id buffer_size, auto emit_func) {
+    Id zero_value{};
+    Id result_type{};
+    if constexpr (bit_size == 64) {
+        zero_value = ctx.u64_zero_value;
+        result_type = ctx.U64;
+    } else if constexpr (bit_size == 32) {
+        zero_value = ctx.u32_zero_value;
+        result_type = ctx.U32[1];
+    } else if constexpr (bit_size == 16) {
+        zero_value = ctx.u16_zero_value;
+        result_type = ctx.U16;
+    } else {
+        static_assert(false, "type not supported");
+    }
+    if (Sirit::ValidId(buffer_size)) {
+        // Bounds checking enabled, wrap in a conditional branch to make sure that
+        // the atomic is not mistakenly executed when the index is out of bounds.
+        const Id in_bounds = ctx.OpULessThan(ctx.U1[1], index, buffer_size);
+        const Id ib_label = ctx.OpLabel();
+        const Id end_label = ctx.OpLabel();
+        ctx.OpSelectionMerge(end_label, spv::SelectionControlMask::MaskNone);
+        ctx.OpBranchConditional(in_bounds, ib_label, end_label);
+        const auto last_label = ctx.last_label;
+        ctx.AddLabel(ib_label);
+        const auto ib_result = emit_func();
+        ctx.OpBranch(end_label);
+        ctx.AddLabel(end_label);
+        if (Sirit::ValidId(ib_result)) {
+            return ctx.OpPhi(result_type, ib_result, ib_label, zero_value, last_label);
+        } else {
+            return Id{0};
+        }
+    }
+    // Bounds checking not enabled, just perform the atomic operation.
+    return emit_func();
+}
+
+} // namespace Shader::Backend::SPIRV

src/shader_recompiler/backend/spirv/emit_spirv_instructions.h

@@ -86,6 +86,7 @@ void EmitStoreBufferF32x3(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addre
 void EmitStoreBufferF32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
 void EmitStoreBufferFormatF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
 Id EmitBufferAtomicIAdd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
+Id EmitBufferAtomicIAdd64(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
 Id EmitBufferAtomicSMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
 Id EmitBufferAtomicUMin32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
 Id EmitBufferAtomicSMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
@@ -120,11 +121,14 @@ Id EmitUndefU8(EmitContext& ctx);
 Id EmitUndefU16(EmitContext& ctx);
 Id EmitUndefU32(EmitContext& ctx);
 Id EmitUndefU64(EmitContext& ctx);
+Id EmitLoadSharedU16(EmitContext& ctx, Id offset);
 Id EmitLoadSharedU32(EmitContext& ctx, Id offset);
 Id EmitLoadSharedU64(EmitContext& ctx, Id offset);
+void EmitWriteSharedU16(EmitContext& ctx, Id offset, Id value);
 void EmitWriteSharedU32(EmitContext& ctx, Id offset, Id value);
 void EmitWriteSharedU64(EmitContext& ctx, Id offset, Id value);
 Id EmitSharedAtomicIAdd32(EmitContext& ctx, Id offset, Id value);
+Id EmitSharedAtomicIAdd64(EmitContext& ctx, Id offset, Id value);
 Id EmitSharedAtomicUMax32(EmitContext& ctx, Id offset, Id value);
 Id EmitSharedAtomicSMax32(EmitContext& ctx, Id offset, Id value);
 Id EmitSharedAtomicUMin32(EmitContext& ctx, Id offset, Id value);

src/shader_recompiler/backend/spirv/emit_spirv_shared_memory.cpp

@@ -1,43 +1,86 @@
 // SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 
+#include "common/div_ceil.h"
+#include "shader_recompiler/backend/spirv/emit_spirv_bounds.h"
 #include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
 #include "shader_recompiler/backend/spirv/spirv_emit_context.h"
 
 namespace Shader::Backend::SPIRV {
 
+Id EmitLoadSharedU16(EmitContext& ctx, Id offset) {
+    const Id shift_id{ctx.ConstU32(1U)};
+    const Id index{ctx.OpShiftRightLogical(ctx.U32[1], offset, shift_id)};
+    const u32 num_elements{Common::DivCeil(ctx.runtime_info.cs_info.shared_memory_size, 2u)};
+
+    return AccessBoundsCheck<16>(ctx, index, ctx.ConstU32(num_elements), [&] {
+        const Id pointer =
+            ctx.OpAccessChain(ctx.shared_u16, ctx.shared_memory_u16, ctx.u32_zero_value, index);
+        return ctx.OpLoad(ctx.U16, pointer);
+    });
+}
+
 Id EmitLoadSharedU32(EmitContext& ctx, Id offset) {
     const Id shift_id{ctx.ConstU32(2U)};
-    const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
-    const Id pointer = ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, index);
-    return ctx.OpLoad(ctx.U32[1], pointer);
+    const Id index{ctx.OpShiftRightLogical(ctx.U32[1], offset, shift_id)};
+    const u32 num_elements{Common::DivCeil(ctx.runtime_info.cs_info.shared_memory_size, 4u)};
+
+    return AccessBoundsCheck<32>(ctx, index, ctx.ConstU32(num_elements), [&] {
+        const Id pointer =
+            ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, ctx.u32_zero_value, index);
+        return ctx.OpLoad(ctx.U32[1], pointer);
+    });
 }
 
 Id EmitLoadSharedU64(EmitContext& ctx, Id offset) {
-    const Id shift_id{ctx.ConstU32(2U)};
-    const Id base_index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
-    const Id next_index{ctx.OpIAdd(ctx.U32[1], base_index, ctx.ConstU32(1U))};
-    const Id lhs_pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, base_index)};
-    const Id rhs_pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, next_index)};
-    return ctx.OpCompositeConstruct(ctx.U32[2], ctx.OpLoad(ctx.U32[1], lhs_pointer),
-                                    ctx.OpLoad(ctx.U32[1], rhs_pointer));
+    const Id shift_id{ctx.ConstU32(3U)};
+    const Id index{ctx.OpShiftRightLogical(ctx.U32[1], offset, shift_id)};
+    const u32 num_elements{Common::DivCeil(ctx.runtime_info.cs_info.shared_memory_size, 8u)};
+
+    return AccessBoundsCheck<64>(ctx, index, ctx.ConstU32(num_elements), [&] {
+        const Id pointer{
+            ctx.OpAccessChain(ctx.shared_u64, ctx.shared_memory_u64, ctx.u32_zero_value, index)};
+        return ctx.OpLoad(ctx.U64, pointer);
+    });
+}
+
+void EmitWriteSharedU16(EmitContext& ctx, Id offset, Id value) {
+    const Id shift{ctx.ConstU32(1U)};
+    const Id index{ctx.OpShiftRightLogical(ctx.U32[1], offset, shift)};
+    const u32 num_elements{Common::DivCeil(ctx.runtime_info.cs_info.shared_memory_size, 2u)};
+
+    AccessBoundsCheck<16>(ctx, index, ctx.ConstU32(num_elements), [&] {
+        const Id pointer =
+            ctx.OpAccessChain(ctx.shared_u16, ctx.shared_memory_u16, ctx.u32_zero_value, index);
+        ctx.OpStore(pointer, value);
+        return Id{0};
+    });
 }
 
 void EmitWriteSharedU32(EmitContext& ctx, Id offset, Id value) {
     const Id shift{ctx.ConstU32(2U)};
-    const Id word_offset{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift)};
-    const Id pointer = ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, word_offset);
-    ctx.OpStore(pointer, value);
+    const Id index{ctx.OpShiftRightLogical(ctx.U32[1], offset, shift)};
+    const u32 num_elements{Common::DivCeil(ctx.runtime_info.cs_info.shared_memory_size, 4u)};
+
+    AccessBoundsCheck<32>(ctx, index, ctx.ConstU32(num_elements), [&] {
+        const Id pointer =
+            ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, ctx.u32_zero_value, index);
+        ctx.OpStore(pointer, value);
+        return Id{0};
+    });
 }
 
 void EmitWriteSharedU64(EmitContext& ctx, Id offset, Id value) {
-    const Id shift{ctx.ConstU32(2U)};
-    const Id word_offset{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift)};
-    const Id next_offset{ctx.OpIAdd(ctx.U32[1], word_offset, ctx.ConstU32(1U))};
-    const Id lhs_pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, word_offset)};
-    const Id rhs_pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, next_offset)};
-    ctx.OpStore(lhs_pointer, ctx.OpCompositeExtract(ctx.U32[1], value, 0U));
-    ctx.OpStore(rhs_pointer, ctx.OpCompositeExtract(ctx.U32[1], value, 1U));
+    const Id shift{ctx.ConstU32(3U)};
+    const Id index{ctx.OpShiftRightLogical(ctx.U32[1], offset, shift)};
+    const u32 num_elements{Common::DivCeil(ctx.runtime_info.cs_info.shared_memory_size, 8u)};
+
+    AccessBoundsCheck<64>(ctx, index, ctx.ConstU32(num_elements), [&] {
+        const Id pointer{
+            ctx.OpAccessChain(ctx.shared_u64, ctx.shared_memory_u64, ctx.u32_zero_value, index)};
+        ctx.OpStore(pointer, value);
+        return Id{0};
+    });
 }
 
 } // namespace Shader::Backend::SPIRV

src/shader_recompiler/backend/spirv/spirv_emit_context.cpp

@@ -146,6 +146,7 @@ void EmitContext::DefineArithmeticTypes() {
     false_value = ConstantFalse(U1[1]);
     u8_one_value = Constant(U8, 1U);
     u8_zero_value = Constant(U8, 0U);
+    u16_zero_value = Constant(U16, 0U);
     u32_one_value = ConstU32(1U);
     u32_zero_value = ConstU32(0U);
     f32_zero_value = ConstF32(0.0f);
@@ -285,6 +286,8 @@ void EmitContext::DefineBufferProperties() {
             Name(buffer.size_shorts, fmt::format("buf{}_short_size", binding));
             buffer.size_dwords = OpShiftRightLogical(U32[1], buffer.size, ConstU32(2U));
             Name(buffer.size_dwords, fmt::format("buf{}_dword_size", binding));
+            buffer.size_qwords = OpShiftRightLogical(U32[1], buffer.size, ConstU32(3U));
+            Name(buffer.size_qwords, fmt::format("buf{}_qword_size", binding));
         }
     }
 }
@@ -979,13 +982,27 @@ void EmitContext::DefineSharedMemory() {
     }
     ASSERT(info.stage == Stage::Compute);
     const u32 shared_memory_size = runtime_info.cs_info.shared_memory_size;
-    const u32 num_elements{Common::DivCeil(shared_memory_size, 4U)};
-    const Id type{TypeArray(U32[1], ConstU32(num_elements))};
-    shared_memory_u32_type = TypePointer(spv::StorageClass::Workgroup, type);
-    shared_u32 = TypePointer(spv::StorageClass::Workgroup, U32[1]);
-    shared_memory_u32 = AddGlobalVariable(shared_memory_u32_type, spv::StorageClass::Workgroup);
-    Name(shared_memory_u32, "shared_mem");
-    interfaces.push_back(shared_memory_u32);
+
+    const auto make_type = [&](Id element_type, u32 element_size) {
+        const u32 num_elements{Common::DivCeil(shared_memory_size, element_size)};
+        const Id array_type{TypeArray(element_type, ConstU32(num_elements))};
+        Decorate(array_type, spv::Decoration::ArrayStride, element_size);
+
+        const Id struct_type{TypeStruct(array_type)};
+        MemberDecorate(struct_type, 0u, spv::Decoration::Offset, 0u);
+        Decorate(struct_type, spv::Decoration::Block);
+
+        const Id pointer = TypePointer(spv::StorageClass::Workgroup, struct_type);
+        const Id element_pointer = TypePointer(spv::StorageClass::Workgroup, element_type);
+        const Id variable = AddGlobalVariable(pointer, spv::StorageClass::Workgroup);
+        Decorate(variable, spv::Decoration::Aliased);
+        interfaces.push_back(variable);
+
+        return std::make_tuple(variable, element_pointer, pointer);
+    };
+    std::tie(shared_memory_u16, shared_u16, shared_memory_u16_type) = make_type(U16, 2u);
+    std::tie(shared_memory_u32, shared_u32, shared_memory_u32_type) = make_type(U32[1], 4u);
+    std::tie(shared_memory_u64, shared_u64, shared_memory_u64_type) = make_type(U64, 8u);
 }
 
 Id EmitContext::DefineFloat32ToUfloatM5(u32 mantissa_bits, const std::string_view name) {

src/shader_recompiler/backend/spirv/spirv_emit_context.h

@@ -235,17 +235,16 @@ public:
     Id false_value{};
     Id u8_one_value{};
     Id u8_zero_value{};
+    Id u16_zero_value{};
     Id u32_one_value{};
     Id u32_zero_value{};
     Id f32_zero_value{};
     Id u64_one_value{};
     Id u64_zero_value{};
 
-    Id shared_u8{};
     Id shared_u16{};
     Id shared_u32{};
-    Id shared_u32x2{};
-    Id shared_u32x4{};
+    Id shared_u64{};
 
     Id input_u32{};
     Id input_f32{};
@@ -285,13 +284,13 @@ public:
     Id image_u32{};
     Id image_f32{};
 
-    Id shared_memory_u8{};
     Id shared_memory_u16{};
     Id shared_memory_u32{};
-    Id shared_memory_u32x2{};
-    Id shared_memory_u32x4{};
+    Id shared_memory_u64{};
 
+    Id shared_memory_u16_type{};
     Id shared_memory_u32_type{};
+    Id shared_memory_u64_type{};
 
     Id bary_coord_persp_id{};
     Id bary_coord_linear_id{};
@@ -320,6 +319,7 @@ public:
         Id size;
         Id size_shorts;
         Id size_dwords;
+        Id size_qwords;
         std::array<BufferSpv, u32(PointerType::NumAlias)> aliases;
 
         const BufferSpv& operator[](PointerType alias) const {