mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-30 23:33:17 +00:00
video_core: Track renderpass scopes properly
This commit is contained in:
parent
ad10020836
commit
22b930ba5e
36 changed files with 400 additions and 166 deletions
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@ -187,6 +187,13 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
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case PM4ItOpcode::ClearState: {
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break;
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}
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case PM4ItOpcode::SetConfigReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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const auto reg_addr = ConfigRegWordOffset + set_data->reg_offset;
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const auto* payload = reinterpret_cast<const u32*>(header + 2);
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std::memcpy(®s.reg_array[reg_addr], payload, (count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::SetContextReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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const auto reg_addr = ContextRegWordOffset + set_data->reg_offset;
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@ -43,6 +43,7 @@ struct Liverpool {
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static constexpr u32 NumShaderUserData = 16;
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static constexpr u32 UconfigRegWordOffset = 0xC000;
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static constexpr u32 ContextRegWordOffset = 0xA000;
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static constexpr u32 ConfigRegWordOffset = 0x2000;
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static constexpr u32 ShRegWordOffset = 0x2C00;
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static constexpr u32 NumRegs = 0xD000;
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@ -789,6 +790,7 @@ struct Liverpool {
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u32 raw;
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BitField<0, 1, u32> depth_clear_enable;
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BitField<1, 1, u32> stencil_clear_enable;
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BitField<6, 1, u32> depth_compress_disable;
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};
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union AaConfig {
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@ -366,6 +366,9 @@ vk::Format SurfaceFormat(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat nu
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if (data_format == AmdGpu::DataFormat::Format8_8 && num_format == AmdGpu::NumberFormat::Unorm) {
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return vk::Format::eR8G8Unorm;
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}
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if (data_format == AmdGpu::DataFormat::FormatBc7 && num_format == AmdGpu::NumberFormat::Unorm) {
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return vk::Format::eBc7UnormBlock;
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}
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if (data_format == AmdGpu::DataFormat::FormatBc2 && num_format == AmdGpu::NumberFormat::Unorm) {
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return vk::Format::eBc2UnormBlock;
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}
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@ -376,9 +379,15 @@ vk::Format SurfaceFormat(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat nu
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if (data_format == AmdGpu::DataFormat::Format2_10_10_10 && num_format == AmdGpu::NumberFormat::Unorm) {
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return vk::Format::eA2R10G10B10UnormPack32;
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}
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if (data_format == AmdGpu::DataFormat::Format2_10_10_10 && num_format == AmdGpu::NumberFormat::Snorm) {
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return vk::Format::eA2R10G10B10SnormPack32;
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}
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if (data_format == AmdGpu::DataFormat::Format10_11_11 && num_format == AmdGpu::NumberFormat::Float) {
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return vk::Format::eB10G11R11UfloatPack32;
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}
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if (data_format == AmdGpu::DataFormat::Format16_16 && num_format == AmdGpu::NumberFormat::Float) {
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return vk::Format::eR16G16Sfloat;
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}
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UNREACHABLE_MSG("Unknown data_format={} and num_format={}", u32(data_format), u32(num_format));
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}
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@ -381,6 +381,7 @@ Frame* RendererVulkan::GetRenderFrame() {
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{
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std::unique_lock lock{free_mutex};
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free_cv.wait(lock, [this] { return !free_queue.empty(); });
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LOG_INFO(Render_Vulkan, "Got render frame, remaining {}", free_queue.size() - 1);
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// Take the frame from the queue
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frame = free_queue.front();
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@ -85,7 +85,7 @@ ComputePipeline::~ComputePipeline() = default;
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bool ComputePipeline::BindResources(Core::MemoryManager* memory, StreamBuffer& staging,
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VideoCore::TextureCache& texture_cache) const {
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// Bind resource buffers and textures.
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boost::container::static_vector<vk::DescriptorBufferInfo, 4> buffer_infos;
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boost::container::static_vector<vk::DescriptorBufferInfo, 8> buffer_infos;
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boost::container::static_vector<vk::DescriptorImageInfo, 8> image_infos;
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boost::container::small_vector<vk::WriteDescriptorSet, 16> set_writes;
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u32 binding{};
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@ -115,7 +115,7 @@ bool ComputePipeline::BindResources(Core::MemoryManager* memory, StreamBuffer& s
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// need its full emulation anyways. For cases of metadata read a warning will be logged.
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if (buffer.is_storage) {
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if (texture_cache.TouchMeta(address, true)) {
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LOG_TRACE(Render_Vulkan, "Metadata update skipped");
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LOG_WARNING(Render_Vulkan, "Metadata update skipped");
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return false;
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}
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} else {
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@ -127,7 +127,7 @@ bool ComputePipeline::BindResources(Core::MemoryManager* memory, StreamBuffer& s
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for (const auto& image : info.images) {
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const auto tsharp = info.ReadUd<AmdGpu::Image>(image.sgpr_base, image.dword_offset);
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const auto& image_view = texture_cache.FindImageView(tsharp, image.is_storage);
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const auto& image_view = texture_cache.FindImageView(tsharp, image.is_storage, image.is_depth);
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image_infos.emplace_back(VK_NULL_HANDLE, *image_view.image_view, vk::ImageLayout::eGeneral);
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set_writes.push_back({
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.dstSet = VK_NULL_HANDLE,
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@ -187,7 +187,7 @@ GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& schedul
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const vk::PipelineRenderingCreateInfoKHR pipeline_rendering_ci = {
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.colorAttachmentCount = num_color_formats,
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.pColorAttachmentFormats = key.color_formats.data(),
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.depthAttachmentFormat = key.depth.depth_enable ? key.depth_format : vk::Format::eUndefined,
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.depthAttachmentFormat = key.depth_format,
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.stencilAttachmentFormat = vk::Format::eUndefined,
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};
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@ -320,7 +320,7 @@ void GraphicsPipeline::BindResources(Core::MemoryManager* memory, StreamBuffer&
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// Bind resource buffers and textures.
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boost::container::static_vector<vk::DescriptorBufferInfo, 16> buffer_infos;
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boost::container::static_vector<vk::DescriptorImageInfo, 16> image_infos;
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boost::container::static_vector<vk::DescriptorImageInfo, 32> image_infos;
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boost::container::small_vector<vk::WriteDescriptorSet, 16> set_writes;
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u32 binding{};
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@ -350,9 +350,10 @@ void GraphicsPipeline::BindResources(Core::MemoryManager* memory, StreamBuffer&
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for (const auto& image : stage.images) {
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const auto tsharp = stage.ReadUd<AmdGpu::Image>(image.sgpr_base, image.dword_offset);
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const auto& image_view = texture_cache.FindImageView(tsharp, image.is_storage);
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const auto& image_view = texture_cache.FindImageView(tsharp, image.is_storage, image.is_depth);
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image_infos.emplace_back(VK_NULL_HANDLE, *image_view.image_view,
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vk::ImageLayout::eShaderReadOnlyOptimal);
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(image.is_storage || image.is_depth) ? vk::ImageLayout::eGeneral
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: vk::ImageLayout::eShaderReadOnlyOptimal);
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set_writes.push_back({
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.dstSet = VK_NULL_HANDLE,
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.dstBinding = binding++,
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@ -205,6 +205,7 @@ bool Instance::CreateDevice() {
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.logicOp = features.logicOp,
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.samplerAnisotropy = features.samplerAnisotropy,
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.fragmentStoresAndAtomics = features.fragmentStoresAndAtomics,
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.shaderImageGatherExtended = true,
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.shaderStorageImageMultisample = true,
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.shaderClipDistance = features.shaderClipDistance,
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},
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@ -117,8 +117,8 @@ void PipelineCache::RefreshGraphicsKey() {
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key.num_samples = regs.aa_config.NumSamples();
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const auto& db = regs.depth_buffer;
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key.depth_format = LiverpoolToVK::DepthFormat(db.z_info.format, db.stencil_info.format);
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if (key.depth.depth_enable) {
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key.depth_format = LiverpoolToVK::DepthFormat(db.z_info.format, db.stencil_info.format);
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key.depth.depth_enable.Assign(key.depth_format != vk::Format::eUndefined);
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}
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@ -206,6 +206,10 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline() {
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block_pool.ReleaseContents();
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inst_pool.ReleaseContents();
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if (hash == 0xa34c48f8) {
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printf("bad\n");
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}
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// Recompile shader to IR.
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try {
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LOG_INFO(Render_Vulkan, "Compiling {} shader {:#x}", stage, hash);
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@ -214,12 +218,11 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline() {
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// Compile IR to SPIR-V
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auto spv_code = Shader::Backend::SPIRV::EmitSPIRV(profile, programs[i], binding);
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stages[i] = CompileSPV(spv_code, instance.GetDevice());
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infos[i] = &programs[i].info;
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if (Config::dumpShaders()) {
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DumpShader(spv_code, hash, stage, "spv");
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}
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stages[i] = CompileSPV(spv_code, instance.GetDevice());
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infos[i] = &programs[i].info;
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} catch (const Shader::Exception& e) {
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UNREACHABLE_MSG("{}", e.what());
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}
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@ -246,22 +249,25 @@ std::unique_ptr<ComputePipeline> PipelineCache::CreateComputePipeline() {
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inst_pool.ReleaseContents();
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// Recompile shader to IR.
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LOG_INFO(Render_Vulkan, "Compiling cs shader {:#x}", compute_key);
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const Shader::Info info =
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MakeShaderInfo(Shader::Stage::Compute, cs_pgm.user_data, liverpool->regs);
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auto program = Shader::TranslateProgram(inst_pool, block_pool, code, std::move(info));
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try {
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LOG_INFO(Render_Vulkan, "Compiling cs shader {:#x}", compute_key);
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const Shader::Info info =
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MakeShaderInfo(Shader::Stage::Compute, cs_pgm.user_data, liverpool->regs);
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auto program = Shader::TranslateProgram(inst_pool, block_pool, code, std::move(info));
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// Compile IR to SPIR-V
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u32 binding{};
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const auto spv_code = Shader::Backend::SPIRV::EmitSPIRV(profile, program, binding);
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const auto module = CompileSPV(spv_code, instance.GetDevice());
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if (Config::dumpShaders()) {
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DumpShader(spv_code, compute_key, Shader::Stage::Compute, "spv");
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// Compile IR to SPIR-V
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u32 binding{};
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const auto spv_code = Shader::Backend::SPIRV::EmitSPIRV(profile, program, binding);
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if (Config::dumpShaders()) {
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DumpShader(spv_code, compute_key, Shader::Stage::Compute, "spv");
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}
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const auto module = CompileSPV(spv_code, instance.GetDevice());
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return std::make_unique<ComputePipeline>(instance, scheduler, *pipeline_cache, &program.info,
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module);
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} catch (const Shader::Exception& e) {
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UNREACHABLE_MSG("{}", e.what());
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return nullptr;
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}
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return std::make_unique<ComputePipeline>(instance, scheduler, *pipeline_cache, &program.info,
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module);
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}
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void PipelineCache::DumpShader(std::span<const u32> code, u64 hash, Shader::Stage stage,
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@ -23,7 +23,7 @@ Rasterizer::Rasterizer(const Instance& instance_, Scheduler& scheduler_,
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: instance{instance_}, scheduler{scheduler_}, texture_cache{texture_cache_},
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liverpool{liverpool_}, memory{Core::Memory::Instance()},
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pipeline_cache{instance, scheduler, liverpool},
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vertex_index_buffer{instance, scheduler, VertexIndexFlags, 128_MB} {
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vertex_index_buffer{instance, scheduler, VertexIndexFlags, 512_MB, BufferType::Upload} {
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if (!Config::nullGpu()) {
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liverpool->BindRasterizer(this);
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}
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@ -46,71 +46,9 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
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pipeline->BindResources(memory, vertex_index_buffer, texture_cache);
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boost::container::static_vector<vk::RenderingAttachmentInfo, Liverpool::NumColorBuffers>
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color_attachments{};
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for (auto col_buf_id = 0u; col_buf_id < Liverpool::NumColorBuffers; ++col_buf_id) {
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const auto& col_buf = regs.color_buffers[col_buf_id];
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if (!col_buf) {
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continue;
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}
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const auto& hint = liverpool->last_cb_extent[col_buf_id];
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const auto& image_view = texture_cache.RenderTarget(col_buf, hint);
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const bool is_clear = texture_cache.IsMetaCleared(col_buf.CmaskAddress());
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color_attachments.push_back({
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.imageView = *image_view.image_view,
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.imageLayout = vk::ImageLayout::eGeneral,
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.loadOp = is_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
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.storeOp = vk::AttachmentStoreOp::eStore,
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.clearValue =
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is_clear ? LiverpoolToVK::ColorBufferClearValue(col_buf) : vk::ClearValue{},
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});
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texture_cache.TouchMeta(col_buf.CmaskAddress(), false);
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}
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vk::RenderingAttachmentInfo depth_attachment{};
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u32 num_depth_attachments{};
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if (pipeline->IsDepthEnabled() && regs.depth_buffer.Address() != 0) {
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const auto htile_address = regs.depth_htile_data_base.GetAddress();
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const bool is_clear = regs.depth_render_control.depth_clear_enable ||
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texture_cache.IsMetaCleared(htile_address);
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const auto& image_view =
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texture_cache.DepthTarget(regs.depth_buffer, htile_address, liverpool->last_db_extent);
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depth_attachment = {
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.imageView = *image_view.image_view,
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.imageLayout = vk::ImageLayout::eGeneral,
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.loadOp = is_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
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.storeOp = is_clear ? vk::AttachmentStoreOp::eNone : vk::AttachmentStoreOp::eStore,
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.clearValue = vk::ClearValue{.depthStencil = {.depth = regs.depth_clear,
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.stencil = regs.stencil_clear}},
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};
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texture_cache.TouchMeta(htile_address, false);
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num_depth_attachments++;
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}
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// TODO: Don't restart renderpass every draw
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const auto& scissor = regs.screen_scissor;
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vk::RenderingInfo rendering_info = {
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.renderArea =
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{
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.offset = {scissor.top_left_x, scissor.top_left_y},
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.extent = {scissor.GetWidth(), scissor.GetHeight()},
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},
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.layerCount = 1,
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.colorAttachmentCount = static_cast<u32>(color_attachments.size()),
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.pColorAttachments = color_attachments.data(),
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.pDepthAttachment = num_depth_attachments ? &depth_attachment : nullptr,
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};
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auto& area = rendering_info.renderArea.extent;
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if (area.width == 2048) {
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area.width = 1920;
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area.height = 1080;
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}
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BeginRendering();
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UpdateDynamicState(*pipeline);
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cmdbuf.beginRendering(rendering_info);
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cmdbuf.bindPipeline(vk::PipelineBindPoint::eGraphics, pipeline->Handle());
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if (is_indexed) {
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cmdbuf.drawIndexed(num_indices, regs.num_instances.NumInstances(), 0, 0, 0);
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@ -120,7 +58,6 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
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: regs.num_indices;
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cmdbuf.draw(num_vertices, regs.num_instances.NumInstances(), 0, 0);
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}
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cmdbuf.endRendering();
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}
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void Rasterizer::DispatchDirect() {
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@ -138,15 +75,66 @@ void Rasterizer::DispatchDirect() {
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return;
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}
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scheduler.EndRendering();
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cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, pipeline->Handle());
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cmdbuf.dispatch(cs_program.dim_x, cs_program.dim_y, cs_program.dim_z);
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}
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void Rasterizer::BeginRendering() {
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const auto& regs = liverpool->regs;
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RenderState state;
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for (auto col_buf_id = 0u; col_buf_id < Liverpool::NumColorBuffers; ++col_buf_id) {
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const auto& col_buf = regs.color_buffers[col_buf_id];
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if (!col_buf) {
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continue;
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}
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const auto& hint = liverpool->last_cb_extent[col_buf_id];
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const auto& image_view = texture_cache.RenderTarget(col_buf, hint);
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state.width = std::min<u32>(state.width, hint.width);
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state.height = std::min<u32>(state.height, hint.height);
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const bool is_clear = texture_cache.IsMetaCleared(col_buf.CmaskAddress());
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state.color_attachments[state.num_color_attachments++] = {
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.imageView = *image_view.image_view,
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.imageLayout = vk::ImageLayout::eGeneral,
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.loadOp = is_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
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.storeOp = vk::AttachmentStoreOp::eStore,
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.clearValue =
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is_clear ? LiverpoolToVK::ColorBufferClearValue(col_buf) : vk::ClearValue{},
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};
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texture_cache.TouchMeta(col_buf.CmaskAddress(), false);
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}
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if (regs.depth_buffer.z_info.format != Liverpool::DepthBuffer::ZFormat::Invald &&
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regs.depth_buffer.Address() != 0) {
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const auto htile_address = regs.depth_htile_data_base.GetAddress();
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const bool is_clear = regs.depth_render_control.depth_clear_enable ||
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texture_cache.IsMetaCleared(htile_address);
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const auto& hint = liverpool->last_db_extent;
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const auto& image_view = texture_cache.DepthTarget(regs.depth_buffer, htile_address, hint);
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state.width = std::min<u32>(state.width, hint.width);
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state.height = std::min<u32>(state.height, hint.height);
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state.depth_attachment = {
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.imageView = *image_view.image_view,
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.imageLayout = vk::ImageLayout::eGeneral,
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.loadOp = is_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
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.storeOp = is_clear ? vk::AttachmentStoreOp::eNone : vk::AttachmentStoreOp::eStore,
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.clearValue = vk::ClearValue{.depthStencil = {.depth = regs.depth_clear,
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.stencil = regs.stencil_clear}},
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};
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texture_cache.TouchMeta(htile_address, false);
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state.num_depth_attachments++;
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}
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scheduler.BeginRendering(state);
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}
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u32 Rasterizer::SetupIndexBuffer(bool& is_indexed, u32 index_offset) {
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// Emulate QuadList primitive type with CPU made index buffer.
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const auto& regs = liverpool->regs;
|
||||
if (liverpool->regs.primitive_type == Liverpool::PrimitiveType::QuadList) {
|
||||
ASSERT_MSG(!is_indexed, "Using QuadList primitive with indexed draw");
|
||||
//ASSERT_MSG(!is_indexed, "Using QuadList primitive with indexed draw");
|
||||
is_indexed = true;
|
||||
|
||||
// Emit indices.
|
||||
|
|
|
@ -37,6 +37,8 @@ private:
|
|||
u32 SetupIndexBuffer(bool& is_indexed, u32 index_offset);
|
||||
void MapMemory(VAddr addr, size_t size);
|
||||
|
||||
void BeginRendering();
|
||||
|
||||
void UpdateDynamicState(const GraphicsPipeline& pipeline);
|
||||
void UpdateViewportScissorState();
|
||||
void UpdateDepthStencilState();
|
||||
|
|
|
@ -18,6 +18,37 @@ Scheduler::~Scheduler() {
|
|||
std::free(profiler_scope);
|
||||
}
|
||||
|
||||
void Scheduler::BeginRendering(const RenderState& new_state) {
|
||||
if (is_rendering && render_state == new_state) {
|
||||
return;
|
||||
}
|
||||
EndRendering();
|
||||
is_rendering = true;
|
||||
render_state = new_state;
|
||||
|
||||
const vk::RenderingInfo rendering_info = {
|
||||
.renderArea = {
|
||||
.offset = {0, 0},
|
||||
.extent = {render_state.width, render_state.height},
|
||||
},
|
||||
.layerCount = 1,
|
||||
.colorAttachmentCount = static_cast<u32>(render_state.color_attachments.size()),
|
||||
.pColorAttachments = render_state.color_attachments.data(),
|
||||
.pDepthAttachment = render_state.num_depth_attachments ?
|
||||
&render_state.depth_attachment : nullptr,
|
||||
};
|
||||
|
||||
current_cmdbuf.beginRendering(rendering_info);
|
||||
}
|
||||
|
||||
void Scheduler::EndRendering() {
|
||||
if (!is_rendering) {
|
||||
return;
|
||||
}
|
||||
is_rendering = false;
|
||||
current_cmdbuf.endRendering();
|
||||
}
|
||||
|
||||
void Scheduler::Flush(vk::Semaphore signal, vk::Semaphore wait) {
|
||||
// When flushing, we only send data to the worker thread; no waiting is necessary.
|
||||
SubmitExecution(signal, wait);
|
||||
|
@ -55,6 +86,7 @@ void Scheduler::AllocateWorkerCommandBuffers() {
|
|||
}
|
||||
|
||||
void Scheduler::SubmitExecution(vk::Semaphore signal_semaphore, vk::Semaphore wait_semaphore) {
|
||||
std::scoped_lock lk{submit_mutex};
|
||||
const u64 signal_value = master_semaphore.NextTick();
|
||||
|
||||
auto* profiler_ctx = instance.GetProfilerContext();
|
||||
|
@ -63,7 +95,7 @@ void Scheduler::SubmitExecution(vk::Semaphore signal_semaphore, vk::Semaphore wa
|
|||
TracyVkCollect(profiler_ctx, current_cmdbuf);
|
||||
}
|
||||
|
||||
std::scoped_lock lk{submit_mutex};
|
||||
EndRendering();
|
||||
master_semaphore.SubmitWork(current_cmdbuf, wait_semaphore, signal_semaphore, signal_value);
|
||||
master_semaphore.Refresh();
|
||||
AllocateWorkerCommandBuffers();
|
||||
|
|
|
@ -4,6 +4,7 @@
|
|||
#pragma once
|
||||
|
||||
#include <condition_variable>
|
||||
#include <boost/container/static_vector.hpp>
|
||||
#include "common/types.h"
|
||||
#include "video_core/renderer_vulkan/vk_master_semaphore.h"
|
||||
#include "video_core/renderer_vulkan/vk_resource_pool.h"
|
||||
|
@ -12,6 +13,19 @@ namespace Vulkan {
|
|||
|
||||
class Instance;
|
||||
|
||||
struct RenderState {
|
||||
std::array<vk::RenderingAttachmentInfo, 8> color_attachments{};
|
||||
vk::RenderingAttachmentInfo depth_attachment{};
|
||||
u32 num_color_attachments{};
|
||||
u32 num_depth_attachments{};
|
||||
u32 width = std::numeric_limits<u32>::max();
|
||||
u32 height = std::numeric_limits<u32>::max();
|
||||
|
||||
bool operator==(const RenderState& other) const noexcept {
|
||||
return std::memcmp(this, &other, sizeof(RenderState)) == 0;
|
||||
}
|
||||
};
|
||||
|
||||
class Scheduler {
|
||||
public:
|
||||
explicit Scheduler(const Instance& instance);
|
||||
|
@ -26,6 +40,12 @@ public:
|
|||
/// Waits for the given tick to trigger on the GPU.
|
||||
void Wait(u64 tick);
|
||||
|
||||
/// Starts a new rendering scope with provided state.
|
||||
void BeginRendering(const RenderState& new_state);
|
||||
|
||||
/// Ends current rendering scope.
|
||||
void EndRendering();
|
||||
|
||||
/// Returns the current command buffer.
|
||||
vk::CommandBuffer CommandBuffer() const {
|
||||
return current_cmdbuf;
|
||||
|
@ -59,6 +79,8 @@ private:
|
|||
CommandPool command_pool;
|
||||
vk::CommandBuffer current_cmdbuf;
|
||||
std::condition_variable_any event_cv;
|
||||
RenderState render_state;
|
||||
bool is_rendering = false;
|
||||
tracy::VkCtxScope* profiler_scope{};
|
||||
};
|
||||
|
||||
|
|
|
@ -221,6 +221,7 @@ Image::Image(const Vulkan::Instance& instance_, Vulkan::Scheduler& scheduler_,
|
|||
: instance{&instance_}, scheduler{&scheduler_}, info{info_},
|
||||
image{instance->GetDevice(), instance->GetAllocator()}, cpu_addr{cpu_addr},
|
||||
cpu_addr_end{cpu_addr + info.guest_size_bytes} {
|
||||
ASSERT(info.pixel_format != vk::Format::eUndefined);
|
||||
vk::ImageCreateFlags flags{vk::ImageCreateFlagBits::eMutableFormat |
|
||||
vk::ImageCreateFlagBits::eExtendedUsage};
|
||||
if (info.type == vk::ImageType::e2D && info.resources.layers >= 6 &&
|
||||
|
@ -272,7 +273,8 @@ Image::Image(const Vulkan::Instance& instance_, Vulkan::Scheduler& scheduler_,
|
|||
Transit(vk::ImageLayout::eGeneral, vk::AccessFlagBits::eNone);
|
||||
}
|
||||
|
||||
void Image::Transit(vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits> dst_mask) {
|
||||
void Image::Transit(vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits> dst_mask,
|
||||
vk::CommandBuffer cmdbuf) {
|
||||
if (dst_layout == layout && dst_mask == access_mask) {
|
||||
return;
|
||||
}
|
||||
|
@ -300,7 +302,12 @@ void Image::Transit(vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits> ds
|
|||
dst_mask == vk::AccessFlagBits::eTransferWrite)
|
||||
? vk::PipelineStageFlagBits::eTransfer
|
||||
: vk::PipelineStageFlagBits::eAllGraphics | vk::PipelineStageFlagBits::eComputeShader;
|
||||
const auto cmdbuf = scheduler->CommandBuffer();
|
||||
|
||||
if (!cmdbuf) {
|
||||
// When using external cmdbuf you are responsible for ending rp.
|
||||
scheduler->EndRendering();
|
||||
cmdbuf = scheduler->CommandBuffer();
|
||||
}
|
||||
cmdbuf.pipelineBarrier(pl_stage, dst_pl_stage, vk::DependencyFlagBits::eByRegion, {}, {},
|
||||
barrier);
|
||||
|
||||
|
@ -310,6 +317,7 @@ void Image::Transit(vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits> ds
|
|||
}
|
||||
|
||||
void Image::Upload(vk::Buffer buffer, u64 offset) {
|
||||
scheduler->EndRendering();
|
||||
Transit(vk::ImageLayout::eTransferDstOptimal, vk::AccessFlagBits::eTransferWrite);
|
||||
|
||||
// Copy to the image.
|
||||
|
@ -318,7 +326,7 @@ void Image::Upload(vk::Buffer buffer, u64 offset) {
|
|||
.bufferRowLength = info.pitch,
|
||||
.bufferImageHeight = info.size.height,
|
||||
.imageSubresource{
|
||||
.aspectMask = vk::ImageAspectFlagBits::eColor,
|
||||
.aspectMask = aspect_mask,
|
||||
.mipLevel = 0,
|
||||
.baseArrayLayer = 0,
|
||||
.layerCount = 1,
|
||||
|
|
|
@ -132,7 +132,8 @@ struct Image {
|
|||
return image_view_ids[std::distance(image_view_infos.begin(), it)];
|
||||
}
|
||||
|
||||
void Transit(vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits> dst_mask);
|
||||
void Transit(vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits> dst_mask,
|
||||
vk::CommandBuffer cmdbuf = {});
|
||||
void Upload(vk::Buffer buffer, u64 offset);
|
||||
|
||||
const Vulkan::Instance* instance;
|
||||
|
|
|
@ -80,8 +80,10 @@ ImageView::ImageView(const Vulkan::Instance& instance, const ImageViewInfo& info
|
|||
|
||||
// When sampling D32 texture from shader, the T# specifies R32 Float format so adjust it.
|
||||
vk::Format format = info.format;
|
||||
vk::ImageAspectFlags aspect = image.aspect_mask;
|
||||
if (image.aspect_mask & vk::ImageAspectFlagBits::eDepth && format == vk::Format::eR32Sfloat) {
|
||||
format = vk::Format::eD32Sfloat;
|
||||
format = image.info.pixel_format;
|
||||
aspect = vk::ImageAspectFlagBits::eDepth;
|
||||
}
|
||||
|
||||
const vk::ImageViewCreateInfo image_view_ci = {
|
||||
|
@ -91,7 +93,7 @@ ImageView::ImageView(const Vulkan::Instance& instance, const ImageViewInfo& info
|
|||
.format = format,
|
||||
.components = info.mapping,
|
||||
.subresourceRange{
|
||||
.aspectMask = image.aspect_mask,
|
||||
.aspectMask = aspect,
|
||||
.baseMipLevel = 0U,
|
||||
.levelCount = 1,
|
||||
.baseArrayLayer = 0,
|
||||
|
|
|
@ -116,10 +116,15 @@ Image& TextureCache::FindImage(const ImageInfo& info, VAddr cpu_address, bool re
|
|||
std::unique_lock lock{m_page_table};
|
||||
boost::container::small_vector<ImageId, 2> image_ids;
|
||||
ForEachImageInRegion(cpu_address, info.guest_size_bytes, [&](ImageId image_id, Image& image) {
|
||||
if (image.cpu_addr == cpu_address && image.info.size.width == info.size.width &&
|
||||
image.info.IsDepthStencil() == info.IsDepthStencil()) {
|
||||
image_ids.push_back(image_id);
|
||||
// Address and width must match.
|
||||
if (image.cpu_addr != cpu_address || image.info.size.width != info.size.width) {
|
||||
return;
|
||||
}
|
||||
if (info.IsDepthStencil() != image.info.IsDepthStencil() &&
|
||||
info.pixel_format != vk::Format::eR32Sfloat) {
|
||||
return;
|
||||
}
|
||||
image_ids.push_back(image_id);
|
||||
});
|
||||
|
||||
ASSERT_MSG(image_ids.size() <= 1, "Overlapping images not allowed!");
|
||||
|
@ -129,7 +134,7 @@ Image& TextureCache::FindImage(const ImageInfo& info, VAddr cpu_address, bool re
|
|||
image_id = slot_images.insert(instance, scheduler, info, cpu_address);
|
||||
RegisterImage(image_id);
|
||||
} else {
|
||||
image_id = image_ids[0];
|
||||
image_id = image_ids.size() > 1 ? image_ids[1] : image_ids[0];
|
||||
}
|
||||
|
||||
RegisterMeta(info, image_id);
|
||||
|
@ -163,11 +168,11 @@ ImageView& TextureCache::RegisterImageView(Image& image, const ImageViewInfo& vi
|
|||
return slot_image_views[view_id];
|
||||
}
|
||||
|
||||
ImageView& TextureCache::FindImageView(const AmdGpu::Image& desc, bool is_storage) {
|
||||
ImageView& TextureCache::FindImageView(const AmdGpu::Image& desc, bool is_storage, bool is_depth) {
|
||||
const ImageInfo info{desc};
|
||||
Image& image = FindImage(info, desc.Address());
|
||||
|
||||
if (is_storage) {
|
||||
if (is_storage || is_depth) {
|
||||
image.Transit(vk::ImageLayout::eGeneral, vk::AccessFlagBits::eShaderWrite);
|
||||
image.info.usage.storage = true;
|
||||
} else {
|
||||
|
@ -202,7 +207,7 @@ ImageView& TextureCache::DepthTarget(const AmdGpu::Liverpool::DepthBuffer& buffe
|
|||
auto& image = FindImage(info, buffer.Address(), false);
|
||||
image.flags &= ~ImageFlagBits::CpuModified;
|
||||
|
||||
image.Transit(vk::ImageLayout::eDepthStencilAttachmentOptimal,
|
||||
image.Transit(vk::ImageLayout::eGeneral,
|
||||
vk::AccessFlagBits::eDepthStencilAttachmentWrite |
|
||||
vk::AccessFlagBits::eDepthStencilAttachmentRead);
|
||||
|
||||
|
@ -261,6 +266,8 @@ void TextureCache::RefreshImage(Image& image) {
|
|||
.imageExtent = {width, height, 1},
|
||||
};
|
||||
|
||||
scheduler.EndRendering();
|
||||
|
||||
const auto cmdbuf = scheduler.CommandBuffer();
|
||||
image.Transit(vk::ImageLayout::eTransferDstOptimal, vk::AccessFlagBits::eTransferWrite);
|
||||
|
||||
|
|
|
@ -52,7 +52,8 @@ public:
|
|||
bool refresh_on_create = true);
|
||||
|
||||
/// Retrieves an image view with the properties of the specified image descriptor.
|
||||
[[nodiscard]] ImageView& FindImageView(const AmdGpu::Image& image, bool is_storage);
|
||||
[[nodiscard]] ImageView& FindImageView(const AmdGpu::Image& image, bool is_storage,
|
||||
bool is_depth);
|
||||
|
||||
/// Retrieves the render target with specified properties
|
||||
[[nodiscard]] ImageView& RenderTarget(const AmdGpu::Liverpool::ColorBuffer& buffer,
|
||||
|
|
|
@ -231,7 +231,7 @@ static constexpr vk::BufferUsageFlags StagingFlags = vk::BufferUsageFlagBits::eT
|
|||
|
||||
TileManager::TileManager(const Vulkan::Instance& instance, Vulkan::Scheduler& scheduler)
|
||||
: instance{instance}, scheduler{scheduler},
|
||||
staging{instance, scheduler, StagingFlags, 64_MB, Vulkan::BufferType::Upload} {
|
||||
staging{instance, scheduler, StagingFlags, 128_MB, Vulkan::BufferType::Upload} {
|
||||
|
||||
static const std::array detiler_shaders{
|
||||
HostShaders::DETILE_M8X1_COMP, HostShaders::DETILE_M8X2_COMP,
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue