mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-19 18:04:56 +00:00
video_core: initial support for CE and ASC queues
This commit is contained in:
psucien
parent
3c90b8ac00
commit
2963790e0d
5 changed files with 413 additions and 159 deletions
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@ -10,6 +10,8 @@
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namespace AmdGpu {
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std::array<u8, 48_KB> Liverpool::ConstantEngine::constants_heap;
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Liverpool::Liverpool() {
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process_thread = std::jthread{std::bind_front(&Liverpool::Process, this)};
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}
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@ -20,169 +22,311 @@ Liverpool::~Liverpool() {
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}
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void Liverpool::Process(std::stop_token stoken) {
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Common::SetCurrentThreadName("GPU_CommandProcessor");
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while (!stoken.stop_requested()) {
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std::span<const u32> dcb{};
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{
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std::unique_lock lock{m_ring_access};
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cv_submit.wait(lock, stoken, [&]() { return !gfx_ring.empty(); });
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if (stoken.stop_requested()) {
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break;
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}
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dcb = gfx_ring.front();
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gfx_ring.pop();
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std::unique_lock lock{m_submit};
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cv_submit.wait(lock, stoken, [this]() { return num_submits != 0; });
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}
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ASSERT_MSG(!dcb.empty(), "Empty command list received");
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ProcessCmdList(dcb.data(), dcb.size_bytes());
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if (stoken.stop_requested()) {
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break;
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}
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{
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std::unique_lock lock{m_ring_access};
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if (gfx_ring.empty()) {
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cv_complete.notify_all();
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int qid = -1;
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while (num_submits) {
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qid = (qid + 1) % NumTotalQueues;
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auto& queue = mapped_queues[qid];
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Task::Handle task{};
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{
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std::scoped_lock lock{queue.m_access};
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if (queue.submits.empty()) {
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continue;
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}
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task = queue.submits.front();
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}
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task.resume();
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if (task.done()) {
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std::scoped_lock lock{queue.m_access};
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queue.submits.pop();
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--num_submits;
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}
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}
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cv_complete.notify_all(); // Notify GPU idle
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}
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}
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void Liverpool::WaitGpuIdle() {
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std::unique_lock lock{m_ring_access};
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cv_complete.wait(lock, [this]() { return gfx_ring.empty(); });
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std::unique_lock lock{m_submit};
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cv_complete.wait(lock, [this]() { return num_submits == 0; });
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}
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void Liverpool::ProcessCmdList(const u32* cmdbuf, u32 size_in_bytes) {
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Common::SetCurrentThreadName("CommandProcessor_Gfx");
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auto* header = reinterpret_cast<const PM4Header*>(cmdbuf);
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u32 processed_cmd_size = 0;
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while (processed_cmd_size < size_in_bytes) {
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const PM4Header* next_header{};
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Liverpool::Task Liverpool::ProcessCeUpdate(std::span<const u32> ccb) {
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while (!ccb.empty()) {
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const auto* header = reinterpret_cast<const PM4Header*>(ccb.data());
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const u32 type = header->type;
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switch (type) {
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case 3: {
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const PM4ItOpcode opcode = header->type3.opcode;
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const u32 count = header->type3.NumWords();
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switch (opcode) {
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case PM4ItOpcode::Nop: {
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const auto* nop = reinterpret_cast<const PM4CmdNop*>(header);
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if (nop->header.count.Value() == 0) {
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break;
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}
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switch (nop->data_block[0]) {
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case PM4CmdNop::PayloadType::PatchedFlip: {
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// There is no evidence that GPU CP drives flip events by parsing
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// special NOP packets. For convenience lets assume that it does.
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Platform::IrqC::Instance()->Signal(Platform::InterruptId::GfxFlip);
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break;
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}
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default:
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break;
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}
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break;
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}
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case PM4ItOpcode::SetContextReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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std::memcpy(®s.reg_array[ContextRegWordOffset + set_data->reg_offset],
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header + 2, (count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::SetShReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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std::memcpy(®s.reg_array[ShRegWordOffset + set_data->reg_offset], header + 2,
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(count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::SetUconfigReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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std::memcpy(®s.reg_array[UconfigRegWordOffset + set_data->reg_offset],
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header + 2, (count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::IndexType: {
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const auto* index_type = reinterpret_cast<const PM4CmdDrawIndexType*>(header);
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regs.index_buffer_type.raw = index_type->raw;
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break;
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}
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case PM4ItOpcode::DrawIndex2: {
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const auto* draw_index = reinterpret_cast<const PM4CmdDrawIndex2*>(header);
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regs.max_index_size = draw_index->max_size;
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regs.index_base_address.base_addr_lo = draw_index->index_base_lo;
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regs.index_base_address.base_addr_hi.Assign(draw_index->index_base_hi);
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regs.num_indices = draw_index->index_count;
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regs.draw_initiator = draw_index->draw_initiator;
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if (rasterizer) {
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rasterizer->Draw(true);
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}
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break;
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}
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case PM4ItOpcode::DrawIndexAuto: {
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const auto* draw_index = reinterpret_cast<const PM4CmdDrawIndexAuto*>(header);
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regs.num_indices = draw_index->index_count;
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regs.draw_initiator = draw_index->draw_initiator;
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if (rasterizer) {
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rasterizer->Draw(false);
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}
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break;
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}
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case PM4ItOpcode::DispatchDirect: {
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// const auto* dispatch_direct = reinterpret_cast<PM4CmdDispatchDirect*>(header);
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break;
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}
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case PM4ItOpcode::EventWriteEos: {
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const auto* event_eos = reinterpret_cast<const PM4CmdEventWriteEos*>(header);
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event_eos->SignalFence();
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break;
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}
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case PM4ItOpcode::EventWriteEop: {
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const auto* event_eop = reinterpret_cast<const PM4CmdEventWriteEop*>(header);
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event_eop->SignalFence();
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break;
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}
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case PM4ItOpcode::DmaData: {
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const auto* dma_data = reinterpret_cast<const PM4DmaData*>(header);
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break;
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}
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case PM4ItOpcode::WriteData: {
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const auto* write_data = reinterpret_cast<const PM4CmdWriteData*>(header);
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ASSERT(write_data->dst_sel.Value() == 2 || write_data->dst_sel.Value() == 5);
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const u32 data_size = (header->type3.count.Value() - 2) * 4;
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if (!write_data->wr_one_addr.Value()) {
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std::memcpy(write_data->Address<void*>(), write_data->data, data_size);
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} else {
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UNREACHABLE();
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}
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break;
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}
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case PM4ItOpcode::AcquireMem: {
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// const auto* acquire_mem = reinterpret_cast<PM4CmdAcquireMem*>(header);
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break;
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}
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case PM4ItOpcode::WaitRegMem: {
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const auto* wait_reg_mem = reinterpret_cast<const PM4CmdWaitRegMem*>(header);
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ASSERT(wait_reg_mem->engine.Value() == PM4CmdWaitRegMem::Engine::Me);
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while (!wait_reg_mem->Test()) {
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using namespace std::chrono_literals;
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std::this_thread::sleep_for(1ms);
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}
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break;
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}
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default:
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UNREACHABLE_MSG("Unknown PM4 type 3 opcode {:#x} with count {}",
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static_cast<u32>(opcode), count);
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}
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next_header = header + header->type3.NumWords() + 1;
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break;
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}
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default:
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if (type != 3) {
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// No other types of packets were spotted so far
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UNREACHABLE_MSG("Invalid PM4 type {}", type);
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}
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processed_cmd_size += uintptr_t(next_header) - uintptr_t(header);
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header = next_header;
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const PM4ItOpcode opcode = header->type3.opcode;
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const auto* it_body = reinterpret_cast<const u32*>(header) + 1;
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switch (opcode) {
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case PM4ItOpcode::Nop: {
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const auto* nop = reinterpret_cast<const PM4CmdNop*>(header);
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break;
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}
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case PM4ItOpcode::WriteConstRam: {
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const auto* write_const = reinterpret_cast<const PM4WriteConstRam*>(header);
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memcpy(cblock.constants_heap.data() + write_const->Offset(), &write_const->data,
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write_const->Size());
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break;
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}
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case PM4ItOpcode::DumpConstRam: {
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const auto* dump_const = reinterpret_cast<const PM4DumpConstRam*>(header);
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memcpy(dump_const->Address<void*>(),
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cblock.constants_heap.data() + dump_const->Offset(), dump_const->Size());
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break;
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}
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case PM4ItOpcode::IncrementCeCounter: {
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++cblock.ce_count;
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break;
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}
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case PM4ItOpcode::WaitOnDeCounterDiff: {
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const auto diff = it_body[0];
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while ((cblock.de_count - cblock.ce_count) >= diff) {
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co_yield {};
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}
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break;
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}
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default:
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const u32 count = header->type3.NumWords();
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UNREACHABLE_MSG("Unknown PM4 type 3 opcode {:#x} with count {}",
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static_cast<u32>(opcode), count);
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}
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ccb = ccb.subspan(header->type3.NumWords() + 1);
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}
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}
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Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<const u32> ccb) {
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cblock.Reset();
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// TODO: potentially, ASCs also can depend on CE and in this case the
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// CE task should be moved into more global scope
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Task ce_task{};
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if (!ccb.empty()) {
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// In case of CCB provided kick off CE asap to have the constant heap ready to use
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ce_task = ProcessCeUpdate(ccb);
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ce_task.handle.resume();
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}
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while (!dcb.empty()) {
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const auto* header = reinterpret_cast<const PM4Header*>(dcb.data());
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const u32 type = header->type;
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if (type != 3) {
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// No other types of packets were spotted so far
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UNREACHABLE_MSG("Invalid PM4 type {}", type);
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}
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const u32 count = header->type3.NumWords();
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const PM4ItOpcode opcode = header->type3.opcode;
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switch (opcode) {
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case PM4ItOpcode::Nop: {
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const auto* nop = reinterpret_cast<const PM4CmdNop*>(header);
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if (nop->header.count.Value() == 0) {
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break;
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}
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switch (nop->data_block[0]) {
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case PM4CmdNop::PayloadType::PatchedFlip: {
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// There is no evidence that GPU CP drives flip events by parsing
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// special NOP packets. For convenience lets assume that it does.
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Platform::IrqC::Instance()->Signal(Platform::InterruptId::GfxFlip);
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break;
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}
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default:
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break;
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}
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break;
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}
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case PM4ItOpcode::SetContextReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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std::memcpy(®s.reg_array[ContextRegWordOffset + set_data->reg_offset], header + 2,
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(count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::SetShReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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std::memcpy(®s.reg_array[ShRegWordOffset + set_data->reg_offset], header + 2,
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(count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::SetUconfigReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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std::memcpy(®s.reg_array[UconfigRegWordOffset + set_data->reg_offset], header + 2,
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(count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::IndexType: {
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const auto* index_type = reinterpret_cast<const PM4CmdDrawIndexType*>(header);
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regs.index_buffer_type.raw = index_type->raw;
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break;
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}
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case PM4ItOpcode::DrawIndex2: {
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const auto* draw_index = reinterpret_cast<const PM4CmdDrawIndex2*>(header);
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regs.max_index_size = draw_index->max_size;
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regs.index_base_address.base_addr_lo = draw_index->index_base_lo;
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regs.index_base_address.base_addr_hi.Assign(draw_index->index_base_hi);
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regs.num_indices = draw_index->index_count;
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regs.draw_initiator = draw_index->draw_initiator;
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if (rasterizer) {
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rasterizer->Draw(true);
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}
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break;
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}
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case PM4ItOpcode::DrawIndexAuto: {
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const auto* draw_index = reinterpret_cast<const PM4CmdDrawIndexAuto*>(header);
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regs.num_indices = draw_index->index_count;
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regs.draw_initiator = draw_index->draw_initiator;
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if (rasterizer) {
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rasterizer->Draw(false);
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}
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break;
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}
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case PM4ItOpcode::DispatchDirect: {
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// const auto* dispatch_direct = reinterpret_cast<PM4CmdDispatchDirect*>(header);
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break;
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}
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case PM4ItOpcode::EventWrite: {
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// const auto* event = reinterpret_cast<const PM4CmdEventWrite*>(header);
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break;
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}
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case PM4ItOpcode::EventWriteEos: {
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const auto* event_eos = reinterpret_cast<const PM4CmdEventWriteEos*>(header);
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event_eos->SignalFence();
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break;
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}
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case PM4ItOpcode::EventWriteEop: {
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const auto* event_eop = reinterpret_cast<const PM4CmdEventWriteEop*>(header);
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event_eop->SignalFence();
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break;
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}
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case PM4ItOpcode::DmaData: {
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const auto* dma_data = reinterpret_cast<const PM4DmaData*>(header);
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break;
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}
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case PM4ItOpcode::WriteData: {
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const auto* write_data = reinterpret_cast<const PM4CmdWriteData*>(header);
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ASSERT(write_data->dst_sel.Value() == 2 || write_data->dst_sel.Value() == 5);
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const u32 data_size = (header->type3.count.Value() - 2) * 4;
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if (!write_data->wr_one_addr.Value()) {
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std::memcpy(write_data->Address<void*>(), write_data->data, data_size);
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} else {
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UNREACHABLE();
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}
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break;
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}
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case PM4ItOpcode::AcquireMem: {
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// const auto* acquire_mem = reinterpret_cast<PM4CmdAcquireMem*>(header);
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break;
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}
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case PM4ItOpcode::WaitRegMem: {
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const auto* wait_reg_mem = reinterpret_cast<const PM4CmdWaitRegMem*>(header);
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ASSERT(wait_reg_mem->engine.Value() == PM4CmdWaitRegMem::Engine::Me);
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while (!wait_reg_mem->Test()) {
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co_yield {};
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}
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break;
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}
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case PM4ItOpcode::IncrementDeCounter: {
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++cblock.de_count;
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break;
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}
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case PM4ItOpcode::WaitOnCeCounter: {
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while (cblock.ce_count <= cblock.de_count) {
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ce_task.handle.resume();
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}
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break;
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}
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default:
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UNREACHABLE_MSG("Unknown PM4 type 3 opcode {:#x} with count {}",
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static_cast<u32>(opcode), count);
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}
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dcb = dcb.subspan(header->type3.NumWords() + 1);
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}
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if (ce_task.handle) {
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ASSERT_MSG(ce_task.handle.done(), "Partially processed CCB");
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}
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}
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Liverpool::Task Liverpool::ProcessCompute(std::span<const u32> acb) {
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while (!acb.empty()) {
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const auto* header = reinterpret_cast<const PM4Header*>(acb.data());
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const u32 type = header->type;
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if (type != 3) {
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// No other types of packets were spotted so far
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UNREACHABLE_MSG("Invalid PM4 type {}", type);
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}
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const u32 count = header->type3.NumWords();
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const PM4ItOpcode opcode = header->type3.opcode;
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const auto* it_body = reinterpret_cast<const u32*>(header) + 1;
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switch (opcode) {
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default:
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UNREACHABLE_MSG("Unknown PM4 type 3 opcode {:#x} with count {}",
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static_cast<u32>(opcode), count);
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}
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acb = acb.subspan(header->type3.NumWords() + 1);
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}
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return {}; // Not a coroutine yet
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}
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void Liverpool::SubmitGfx(std::span<const u32> dcb, std::span<const u32> ccb) {
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static constexpr u32 GfxQueueId = 0u;
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auto& queue = mapped_queues[GfxQueueId];
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auto task = ProcessGraphics(dcb, ccb);
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{
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std::unique_lock lock{queue.m_access};
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queue.submits.emplace(task.handle);
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}
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{
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std::unique_lock lock{m_submit};
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++num_submits;
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}
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cv_submit.notify_one();
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}
|
||||
|
||||
void Liverpool::SubmitAsc(u32 vqid, std::span<const u32> acb) {
|
||||
ASSERT_MSG(vqid > 0 && vqid < NumTotalQueues, "Invalid virtual ASC queue index");
|
||||
auto& queue = mapped_queues[vqid];
|
||||
|
||||
const auto& task = ProcessCompute(acb);
|
||||
{
|
||||
std::unique_lock lock{queue.m_access};
|
||||
queue.submits.emplace(task.handle);
|
||||
}
|
||||
|
||||
{
|
||||
std::unique_lock lock{m_submit};
|
||||
++num_submits;
|
||||
}
|
||||
cv_submit.notify_one();
|
||||
}
|
||||
|
||||
} // namespace AmdGpu
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue