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https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-19 01:44:53 +00:00
video_core: Bringup some basic functionality (#145)
* video_core: Remove hack in rasterizer * The hack was to skip the first draw as the display buffer had not been created yet and the texture cache couldn't create one itself. With this patch it now can, using the color buffer parameters from registers * shader_recompiler: Implement attribute loads/stores * video_core: Add basic vertex, index buffer handling and pipeline caching * externals: Make xxhash lowercase
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commit
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50 changed files with 1030 additions and 383 deletions
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@ -171,7 +171,7 @@ Id DefineMain(EmitContext& ctx, IR::Program& program) {
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void DefineEntryPoint(const IR::Program& program, EmitContext& ctx, Id main) {
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const std::span interfaces(ctx.interfaces.data(), ctx.interfaces.size());
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spv::ExecutionModel execution_model{};
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switch (program.stage) {
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switch (program.info.stage) {
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case Stage::Compute: {
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// const std::array<u32, 3> workgroup_size{program.workgroup_size};
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// execution_model = spv::ExecutionModel::GLCompute;
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@ -194,7 +194,7 @@ void DefineEntryPoint(const IR::Program& program, EmitContext& ctx, Id main) {
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// }
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break;
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default:
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throw NotImplementedException("Stage {}", u32(program.stage));
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throw NotImplementedException("Stage {}", u32(program.info.stage));
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}
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ctx.AddEntryPoint(execution_model, main, "main", interfaces);
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}
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@ -222,7 +222,7 @@ std::vector<u32> EmitSPIRV(const Profile& profile, IR::Program& program, Binding
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EmitContext ctx{profile, program, bindings};
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const Id main{DefineMain(ctx, program)};
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DefineEntryPoint(program, ctx, main);
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if (program.stage == Stage::Vertex) {
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if (program.info.stage == Stage::Vertex) {
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ctx.AddExtension("SPV_KHR_shader_draw_parameters");
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ctx.AddCapability(spv::Capability::DrawParameters);
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}
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@ -10,12 +10,11 @@ namespace {
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Id OutputAttrPointer(EmitContext& ctx, IR::Attribute attr, u32 element) {
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if (IR::IsParam(attr)) {
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const u32 index{u32(attr) - u32(IR::Attribute::Param0)};
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const auto& info{ctx.output_params.at(index).at(element)};
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const auto& info{ctx.output_params.at(index)};
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if (info.num_components == 1) {
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return info.id;
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} else {
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const u32 index_element{element - info.first_element};
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return ctx.OpAccessChain(ctx.output_f32, info.id, ctx.ConstU32(index_element));
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return ctx.OpAccessChain(ctx.output_f32, info.id, ctx.ConstU32(element));
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}
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}
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switch (attr) {
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@ -68,22 +67,21 @@ Id EmitReadConstBufferF32(EmitContext& ctx, const IR::Value& binding, const IR::
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throw LogicError("Unreachable instruction");
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}
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Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, Id vertex) {
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const u32 element{static_cast<u32>(attr) % 4};
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Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp) {
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if (IR::IsParam(attr)) {
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const u32 index{u32(attr) - u32(IR::Attribute::Param0)};
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const auto& param{ctx.input_params.at(index)};
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if (!ValidId(param.id)) {
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// Attribute is disabled or varying component is not written
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return ctx.ConstF32(element == 3 ? 1.0f : 0.0f);
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return ctx.ConstF32(comp == 3 ? 1.0f : 0.0f);
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}
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const Id pointer{ctx.OpAccessChain(param.pointer_type, param.id, ctx.ConstU32(element))};
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const Id pointer{ctx.OpAccessChain(param.pointer_type, param.id, ctx.ConstU32(comp))};
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return ctx.OpLoad(param.component_type, pointer);
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}
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throw NotImplementedException("Read attribute {}", attr);
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}
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Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, Id) {
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Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, u32 comp) {
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switch (attr) {
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case IR::Attribute::VertexId:
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return ctx.OpLoad(ctx.U32[1], ctx.vertex_index);
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@ -93,9 +91,6 @@ Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, Id) {
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}
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void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, u32 element) {
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if (attr == IR::Attribute::Param0) {
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return;
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}
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const Id pointer{OutputAttrPointer(ctx, attr, element)};
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ctx.OpStore(pointer, value);
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}
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@ -46,9 +46,9 @@ Id EmitReadConstBuffer(EmitContext& ctx, const IR::Value& handle, const IR::Valu
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const IR::Value& offset);
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Id EmitReadConstBufferF32(EmitContext& ctx, const IR::Value& handle, const IR::Value& index,
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const IR::Value& offset);
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Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, Id vertex);
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Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, Id vertex);
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void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, u32 element);
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Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp);
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Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, u32 comp);
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void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, u32 comp);
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void EmitSetFragColor(EmitContext& ctx, u32 index, u32 component, Id value);
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void EmitSetSampleMask(EmitContext& ctx, Id value);
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void EmitSetFragDepth(EmitContext& ctx, Id value);
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@ -36,7 +36,7 @@ void Name(EmitContext& ctx, Id object, std::string_view format_str, Args&&... ar
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} // Anonymous namespace
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EmitContext::EmitContext(const Profile& profile_, IR::Program& program, Bindings& bindings)
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: Sirit::Module(profile_.supported_spirv), profile{profile_}, stage{program.stage} {
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: Sirit::Module(profile_.supported_spirv), profile{profile_}, stage{program.info.stage} {
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u32& uniform_binding{bindings.unified};
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u32& storage_binding{bindings.unified};
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u32& texture_binding{bindings.unified};
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@ -98,6 +98,10 @@ void EmitContext::DefineArithmeticTypes() {
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u32_zero_value = ConstU32(0U);
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f32_zero_value = ConstF32(0.0f);
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input_f32 = Name(TypePointer(spv::StorageClass::Input, F32[1]), "input_f32");
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input_u32 = Name(TypePointer(spv::StorageClass::Input, U32[1]), "input_u32");
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input_s32 = Name(TypePointer(spv::StorageClass::Input, S32[1]), "input_s32");
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output_f32 = Name(TypePointer(spv::StorageClass::Output, F32[1]), "output_f32");
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output_u32 = Name(TypePointer(spv::StorageClass::Output, U32[1]), "output_u32");
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}
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@ -107,26 +111,123 @@ void EmitContext::DefineInterfaces(const IR::Program& program) {
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DefineOutputs(program);
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}
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Id GetAttributeType(EmitContext& ctx, AmdGpu::NumberFormat fmt) {
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switch (fmt) {
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case AmdGpu::NumberFormat::Float:
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case AmdGpu::NumberFormat::Unorm:
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return ctx.F32[4];
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case AmdGpu::NumberFormat::Sint:
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return ctx.S32[4];
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case AmdGpu::NumberFormat::Uint:
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return ctx.U32[4];
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case AmdGpu::NumberFormat::Sscaled:
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return ctx.F32[4];
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case AmdGpu::NumberFormat::Uscaled:
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return ctx.F32[4];
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default:
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break;
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}
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throw InvalidArgument("Invalid attribute type {}", fmt);
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}
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EmitContext::SpirvAttribute EmitContext::GetAttributeInfo(AmdGpu::NumberFormat fmt, Id id) {
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switch (fmt) {
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case AmdGpu::NumberFormat::Float:
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case AmdGpu::NumberFormat::Unorm:
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return {id, input_f32, F32[1], 4};
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case AmdGpu::NumberFormat::Uint:
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return {id, input_u32, U32[1], 4};
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case AmdGpu::NumberFormat::Sint:
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return {id, input_s32, S32[1], 4};
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case AmdGpu::NumberFormat::Sscaled:
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return {id, input_f32, F32[1], 4};
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case AmdGpu::NumberFormat::Uscaled:
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return {id, input_f32, F32[1], 4};
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default:
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break;
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}
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throw InvalidArgument("Invalid attribute type {}", fmt);
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}
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Id MakeDefaultValue(EmitContext& ctx, u32 default_value) {
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switch (default_value) {
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case 0:
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return ctx.ConstF32(0.f, 0.f, 0.f, 0.f);
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case 1:
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return ctx.ConstF32(0.f, 0.f, 0.f, 1.f);
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case 2:
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return ctx.ConstF32(1.f, 1.f, 1.f, 0.f);
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case 3:
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return ctx.ConstF32(1.f, 1.f, 1.f, 1.f);
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default:
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UNREACHABLE();
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}
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}
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void EmitContext::DefineInputs(const IR::Program& program) {
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const auto& info = program.info;
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switch (stage) {
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case Stage::Vertex:
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vertex_index = DefineVariable(U32[1], spv::BuiltIn::VertexIndex, spv::StorageClass::Input);
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base_vertex = DefineVariable(U32[1], spv::BuiltIn::BaseVertex, spv::StorageClass::Input);
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for (const auto& input : info.vs_inputs) {
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const Id type{GetAttributeType(*this, input.fmt)};
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const Id id{DefineInput(type, input.binding)};
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Name(id, fmt::format("vs_in_attr{}", input.binding));
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input_params[input.binding] = GetAttributeInfo(input.fmt, id);
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interfaces.push_back(id);
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}
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break;
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case Stage::Fragment:
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for (const auto& input : info.ps_inputs) {
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if (input.is_default) {
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input_params[input.semantic] = {MakeDefaultValue(*this, input.default_value),
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input_f32, F32[1]};
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continue;
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}
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const IR::Attribute param{IR::Attribute::Param0 + input.param_index};
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const u32 num_components = info.loads.NumComponents(param);
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const Id type{F32[num_components]};
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const Id id{DefineInput(type, input.semantic)};
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if (input.is_flat) {
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Decorate(id, spv::Decoration::Flat);
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}
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Name(id, fmt::format("fs_in_attr{}", input.semantic));
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input_params[input.semantic] = {id, input_f32, F32[1], num_components};
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interfaces.push_back(id);
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}
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default:
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break;
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}
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}
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void EmitContext::DefineOutputs(const IR::Program& program) {
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const auto& info = program.info;
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switch (stage) {
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case Stage::Vertex:
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output_position = DefineVariable(F32[4], spv::BuiltIn::Position, spv::StorageClass::Output);
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for (u32 i = 0; i < IR::NumParams; i++) {
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const IR::Attribute param{IR::Attribute::Param0 + i};
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if (!info.stores.GetAny(param)) {
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continue;
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}
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const u32 num_components = info.stores.NumComponents(param);
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const Id id{DefineOutput(F32[num_components], i)};
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Name(id, fmt::format("out_attr{}", i));
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output_params[i] = {id, output_f32, F32[1], num_components};
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interfaces.push_back(id);
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}
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break;
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case Stage::Fragment:
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frag_color[0] = DefineOutput(F32[4], 0);
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Name(frag_color[0], fmt::format("frag_color{}", 0));
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interfaces.push_back(frag_color[0]);
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for (u32 i = 0; i < IR::NumRenderTargets; i++) {
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const IR::Attribute mrt{IR::Attribute::RenderTarget0 + i};
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if (!info.stores.GetAny(mrt)) {
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continue;
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}
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frag_color[i] = DefineOutput(F32[4], i);
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Name(frag_color[i], fmt::format("frag_color{}", i));
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interfaces.push_back(frag_color[i]);
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}
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break;
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default:
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break;
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@ -135,6 +135,9 @@ public:
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Id u32_zero_value{};
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Id f32_zero_value{};
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Id input_u32{};
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Id input_f32{};
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Id input_s32{};
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Id output_u32{};
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Id output_f32{};
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@ -145,25 +148,22 @@ public:
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Id base_vertex{};
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std::array<Id, 8> frag_color{};
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struct InputParamInfo {
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struct SpirvAttribute {
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Id id;
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Id pointer_type;
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Id component_type;
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u32 num_components;
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};
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std::array<InputParamInfo, 32> input_params{};
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struct ParamElementInfo {
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Id id{};
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u32 first_element{};
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u32 num_components{};
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};
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std::array<std::array<ParamElementInfo, 4>, 32> output_params{};
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std::array<SpirvAttribute, 32> input_params{};
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std::array<SpirvAttribute, 32> output_params{};
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private:
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void DefineArithmeticTypes();
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void DefineInterfaces(const IR::Program& program);
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void DefineInputs(const IR::Program& program);
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void DefineOutputs(const IR::Program& program);
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SpirvAttribute GetAttributeInfo(AmdGpu::NumberFormat fmt, Id id);
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};
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} // namespace Shader::Backend::SPIRV
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