video_core: Bringup some basic functionality (#145)

* video_core: Remove hack in rasterizer

* The hack was to skip the first draw as the display buffer had not been created yet and the texture cache couldn't create one itself. With this patch it now can, using the color buffer parameters from registers

* shader_recompiler: Implement attribute loads/stores

* video_core: Add basic vertex, index buffer handling and pipeline caching

* externals: Make xxhash lowercase

src/shader_recompiler/frontend/fetch_shader.cpp

@@ -0,0 +1,83 @@
+// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <boost/container/static_vector.hpp>
+#include "shader_recompiler/frontend/decode.h"
+#include "shader_recompiler/frontend/fetch_shader.h"
+
+namespace Shader::Gcn {
+
+/**
+ * s_load_dwordx4 s[8:11], s[2:3], 0x00
+ * s_load_dwordx4 s[12:15], s[2:3], 0x04
+ * s_load_dwordx4 s[16:19], s[2:3], 0x08
+ * s_waitcnt     lgkmcnt(0)
+ * buffer_load_format_xyzw v[4:7], v0, s[8:11], 0 idxen
+ * buffer_load_format_xyz v[8:10], v0, s[12:15], 0 idxen
+ * buffer_load_format_xy v[12:13], v0, s[16:19], 0 idxen
+ * s_waitcnt     0
+ * s_setpc_b64   s[0:1]
+
+ * s_load_dwordx4  s[4:7], s[2:3], 0x0
+ * s_waitcnt       lgkmcnt(0)
+ * buffer_load_format_xyzw v[4:7], v0, s[4:7], 0 idxen
+ * s_load_dwordx4  s[4:7], s[2:3], 0x8
+ * s_waitcnt       lgkmcnt(0)
+ * buffer_load_format_xyzw v[8:11], v0, s[4:7], 0 idxen
+ * s_waitcnt       vmcnt(0) & expcnt(0) & lgkmcnt(0)
+ * s_setpc_b64     s[0:1]
+
+ * A normal fetch shader looks like the above, the instructions are generated
+ * using input semantics on cpu side. Load instructions can either be separate or interleaved
+ * We take the reverse way, extract the original input semantics from these instructions.
+ **/
+
+std::vector<VertexAttribute> ParseFetchShader(const u32* code) {
+    std::vector<VertexAttribute> attributes;
+    GcnCodeSlice code_slice(code, code + std::numeric_limits<u32>::max());
+    GcnDecodeContext decoder;
+
+    struct VsharpLoad {
+        u32 dword_offset{};
+        s32 base_sgpr{};
+        s32 dst_reg{-1};
+    };
+    boost::container::static_vector<VsharpLoad, 16> loads;
+
+    u32 semantic_index = 0;
+    while (!code_slice.atEnd()) {
+        const auto inst = decoder.decodeInstruction(code_slice);
+        if (inst.opcode == Opcode::S_SETPC_B64) {
+            break;
+        }
+
+        if (inst.inst_class == InstClass::ScalarMemRd) {
+            loads.emplace_back(inst.control.smrd.offset, inst.src[0].code * 2, inst.dst[0].code);
+            continue;
+        }
+
+        if (inst.inst_class == InstClass::VectorMemBufFmt) {
+            // SRSRC is in units of 4 SPGRs while SBASE is in pairs of SGPRs
+            const u32 base_sgpr = inst.src[2].code * 4;
+
+            // Find the load instruction that loaded the V# to the SPGR.
+            // This is so we can determine its index in the vertex table.
+            const auto it = std::ranges::find_if(
+                loads, [&](VsharpLoad& load) { return load.dst_reg == base_sgpr; });
+
+            auto& attrib = attributes.emplace_back();
+            attrib.semantic = semantic_index++;
+            attrib.dest_vgpr = inst.src[1].code;
+            attrib.num_elements = inst.control.mubuf.count;
+            attrib.sgpr_base = it->base_sgpr;
+            attrib.dword_offset = it->dword_offset;
+
+            // Mark load as used.
+            it->dst_reg = -1;
+        }
+    }
+
+    return attributes;
+}
+
+} // namespace Shader::Gcn

src/shader_recompiler/frontend/fetch_shader.h

@@ -0,0 +1,21 @@
+// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include <vector>
+#include "common/types.h"
+
+namespace Shader::Gcn {
+
+struct VertexAttribute {
+    u8 semantic;     ///< Semantic index of the attribute
+    u8 dest_vgpr;    ///< Destination VGPR to load first component.
+    u8 num_elements; ///< Number of components to load
+    u8 sgpr_base;    ///< SGPR that contains the pointer to the list of vertex V#
+    u8 dword_offset; ///< The dword offset of the V# that describes this attribute.
+};
+
+std::vector<VertexAttribute> ParseFetchShader(const u32* code);
+
+} // namespace Shader::Gcn

src/shader_recompiler/frontend/structured_control_flow.cpp

@@ -600,9 +600,9 @@ public:
     TranslatePass(ObjectPool<IR::Inst>& inst_pool_, ObjectPool<IR::Block>& block_pool_,
                   ObjectPool<Statement>& stmt_pool_, Statement& root_stmt,
                   IR::AbstractSyntaxList& syntax_list_, std::span<const GcnInst> inst_list_,
-                  Stage stage_)
+                  Info& info_)
         : stmt_pool{stmt_pool_}, inst_pool{inst_pool_}, block_pool{block_pool_},
-          syntax_list{syntax_list_}, inst_list{inst_list_}, stage{stage_} {
+          syntax_list{syntax_list_}, inst_list{inst_list_}, info{info_} {
         Visit(root_stmt, nullptr, nullptr);
 
         IR::Block& first_block{*syntax_list.front().data.block};
@@ -633,8 +633,7 @@ private:
                 ensure_block();
                 const u32 start = stmt.block->begin_index;
                 const u32 size = stmt.block->end_index - start + 1;
-                Translate(current_block, stage, inst_list.subspan(start, size));
-                fmt::print("{}\n", IR::DumpBlock(*current_block));
+                Translate(current_block, inst_list.subspan(start, size), info);
                 break;
             }
             case StatementType::SetVariable: {
@@ -812,17 +811,17 @@ private:
     IR::AbstractSyntaxList& syntax_list;
     const Block dummy_flow_block{};
     std::span<const GcnInst> inst_list;
-    Stage stage;
+    Info& info;
 };
 } // Anonymous namespace
 
 IR::AbstractSyntaxList BuildASL(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Block>& block_pool,
-                                CFG& cfg, Stage stage) {
+                                CFG& cfg, Info& info) {
     ObjectPool<Statement> stmt_pool{64};
     GotoPass goto_pass{cfg, stmt_pool};
     Statement& root{goto_pass.RootStatement()};
     IR::AbstractSyntaxList syntax_list;
-    TranslatePass{inst_pool, block_pool, stmt_pool, root, syntax_list, cfg.inst_list, stage};
+    TranslatePass{inst_pool, block_pool, stmt_pool, root, syntax_list, cfg.inst_list, info};
     return syntax_list;
 }
 

src/shader_recompiler/frontend/structured_control_flow.h

@@ -10,13 +10,13 @@
 #include "shader_recompiler/object_pool.h"
 
 namespace Shader {
-enum class Stage : u32;
+struct Info;
 }
 
 namespace Shader::Gcn {
 
 [[nodiscard]] IR::AbstractSyntaxList BuildASL(ObjectPool<IR::Inst>& inst_pool,
                                               ObjectPool<IR::Block>& block_pool, CFG& cfg,
-                                              Stage stage);
+                                              Info& info);
 
 } // namespace Shader::Gcn

src/shader_recompiler/frontend/translate/translate.cpp

@@ -2,14 +2,16 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 
 #include "shader_recompiler/exception.h"
+#include "shader_recompiler/frontend/fetch_shader.h"
 #include "shader_recompiler/frontend/translate/translate.h"
 #include "shader_recompiler/runtime_info.h"
+#include "video_core/amdgpu/resource.h"
 
 namespace Shader::Gcn {
 
-Translator::Translator(IR::Block* block_, Stage stage) : block{block_}, ir{*block} {
+Translator::Translator(IR::Block* block_, Info& info_) : block{block_}, ir{*block}, info{info_} {
     IR::VectorReg dst_vreg = IR::VectorReg::V0;
-    switch (stage) {
+    switch (info.stage) {
     case Stage::Vertex:
         // https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L146C1-L146C23
         ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
@@ -92,11 +94,39 @@ void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
     }
 }
 
-void Translate(IR::Block* block, Stage stage, std::span<const GcnInst> inst_list) {
+void Translator::EmitFetch(const GcnInst& inst) {
+    // Read the pointer to the fetch shader assembly.
+    const u32 sgpr_base = inst.src[0].code;
+    const u32* code;
+    std::memcpy(&code, &info.user_data[sgpr_base], sizeof(code));
+
+    // Parse the assembly to generate a list of attributes.
+    const auto attribs = ParseFetchShader(code);
+    for (const auto& attrib : attribs) {
+        const IR::Attribute attr{IR::Attribute::Param0 + attrib.semantic};
+        IR::VectorReg dst_reg{attrib.dest_vgpr};
+        for (u32 i = 0; i < attrib.num_elements; i++) {
+            ir.SetVectorReg(dst_reg++, ir.GetAttribute(attr, i));
+        }
+
+        // Read the V# of the attribute to figure out component number and type.
+        const auto buffer = info.ReadUd<AmdGpu::Buffer>(attrib.sgpr_base, attrib.dword_offset);
+        const u32 num_components = AmdGpu::NumComponents(buffer.data_format);
+        info.vs_inputs.push_back({
+            .fmt = buffer.num_format,
+            .binding = attrib.semantic,
+            .num_components = std::min<u16>(attrib.num_elements, num_components),
+            .sgpr_base = attrib.sgpr_base,
+            .dword_offset = attrib.dword_offset,
+        });
+    }
+}
+
+void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info) {
     if (inst_list.empty()) {
         return;
     }
-    Translator translator{block, stage};
+    Translator translator{block, info};
     for (const auto& inst : inst_list) {
         switch (inst.opcode) {
         case Opcode::S_MOV_B32:
@@ -115,6 +145,9 @@ void Translate(IR::Block* block, Stage stage, std::span<const GcnInst> inst_list
             translator.V_MUL_F32(inst);
             break;
         case Opcode::S_SWAPPC_B64:
+            ASSERT(info.stage == Stage::Vertex);
+            translator.EmitFetch(inst);
+            break;
         case Opcode::S_WAITCNT:
             break; // Ignore for now.
         case Opcode::S_BUFFER_LOAD_DWORDX16:

src/shader_recompiler/frontend/translate/translate.h

@@ -7,9 +7,10 @@
 #include "shader_recompiler/frontend/instruction.h"
 #include "shader_recompiler/ir/basic_block.h"
 #include "shader_recompiler/ir/ir_emitter.h"
+#include "shader_recompiler/runtime_info.h"
 
 namespace Shader {
-enum class Stage : u32;
+struct Info;
 }
 
 namespace Shader::Gcn {
@@ -25,7 +26,9 @@ enum class ConditionOp : u32 {
 
 class Translator {
 public:
-    explicit Translator(IR::Block* block_, Stage stage);
+    explicit Translator(IR::Block* block_, Info& info);
+
+    void EmitFetch(const GcnInst& inst);
 
     // Scalar ALU
     void S_MOV(const GcnInst& inst);
@@ -66,8 +69,9 @@ private:
 private:
     IR::Block* block;
     IR::IREmitter ir;
+    Info& info;
 };
 
-void Translate(IR::Block* block, Stage stage, std::span<const GcnInst> inst_list);
+void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info);
 
 } // namespace Shader::Gcn

src/shader_recompiler/frontend/translate/vector_alu.cpp

@@ -20,9 +20,8 @@ void Translator::V_MAC_F32(const GcnInst& inst) {
 
 void Translator::V_CVT_PKRTZ_F16_F32(const GcnInst& inst) {
     const IR::VectorReg dst_reg{inst.dst[0].code};
-    const IR::Value vec_f32 = ir.CompositeConstruct(ir.FPConvert(16, GetSrc(inst.src[0])),
-                                                    ir.FPConvert(16, GetSrc(inst.src[1])));
-    ir.SetVectorReg(dst_reg, ir.PackFloat2x16(vec_f32));
+    const IR::Value vec_f32 = ir.CompositeConstruct(GetSrc(inst.src[0]), GetSrc(inst.src[1]));
+    ir.SetVectorReg(dst_reg, ir.PackHalf2x16(vec_f32));
 }
 
 void Translator::V_MUL_F32(const GcnInst& inst) {

src/shader_recompiler/frontend/translate/vector_interpolation.cpp

@@ -7,7 +7,9 @@ namespace Shader::Gcn {
 
 void Translator::V_INTERP_P2_F32(const GcnInst& inst) {
     const IR::VectorReg dst_reg{inst.dst[0].code};
-    const IR::Attribute attrib{IR::Attribute::Param0 + inst.control.vintrp.attr};
+    auto& attr = info.ps_inputs.at(inst.control.vintrp.attr);
+    attr.semantic = inst.control.vintrp.attr;
+    const IR::Attribute attrib{IR::Attribute::Param0 + attr.param_index};
     ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
 }