video_core: Bringup some basic functionality (#145)

* video_core: Remove hack in rasterizer

* The hack was to skip the first draw as the display buffer had not been created yet and the texture cache couldn't create one itself. With this patch it now can, using the color buffer parameters from registers

* shader_recompiler: Implement attribute loads/stores

* video_core: Add basic vertex, index buffer handling and pipeline caching

* externals: Make xxhash lowercase

src/shader_recompiler/frontend/translate/translate.cpp

@@ -2,14 +2,16 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 
 #include "shader_recompiler/exception.h"
+#include "shader_recompiler/frontend/fetch_shader.h"
 #include "shader_recompiler/frontend/translate/translate.h"
 #include "shader_recompiler/runtime_info.h"
+#include "video_core/amdgpu/resource.h"
 
 namespace Shader::Gcn {
 
-Translator::Translator(IR::Block* block_, Stage stage) : block{block_}, ir{*block} {
+Translator::Translator(IR::Block* block_, Info& info_) : block{block_}, ir{*block}, info{info_} {
     IR::VectorReg dst_vreg = IR::VectorReg::V0;
-    switch (stage) {
+    switch (info.stage) {
     case Stage::Vertex:
         // https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L146C1-L146C23
         ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
@@ -92,11 +94,39 @@ void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
     }
 }
 
-void Translate(IR::Block* block, Stage stage, std::span<const GcnInst> inst_list) {
+void Translator::EmitFetch(const GcnInst& inst) {
+    // Read the pointer to the fetch shader assembly.
+    const u32 sgpr_base = inst.src[0].code;
+    const u32* code;
+    std::memcpy(&code, &info.user_data[sgpr_base], sizeof(code));
+
+    // Parse the assembly to generate a list of attributes.
+    const auto attribs = ParseFetchShader(code);
+    for (const auto& attrib : attribs) {
+        const IR::Attribute attr{IR::Attribute::Param0 + attrib.semantic};
+        IR::VectorReg dst_reg{attrib.dest_vgpr};
+        for (u32 i = 0; i < attrib.num_elements; i++) {
+            ir.SetVectorReg(dst_reg++, ir.GetAttribute(attr, i));
+        }
+
+        // Read the V# of the attribute to figure out component number and type.
+        const auto buffer = info.ReadUd<AmdGpu::Buffer>(attrib.sgpr_base, attrib.dword_offset);
+        const u32 num_components = AmdGpu::NumComponents(buffer.data_format);
+        info.vs_inputs.push_back({
+            .fmt = buffer.num_format,
+            .binding = attrib.semantic,
+            .num_components = std::min<u16>(attrib.num_elements, num_components),
+            .sgpr_base = attrib.sgpr_base,
+            .dword_offset = attrib.dword_offset,
+        });
+    }
+}
+
+void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info) {
     if (inst_list.empty()) {
         return;
     }
-    Translator translator{block, stage};
+    Translator translator{block, info};
     for (const auto& inst : inst_list) {
         switch (inst.opcode) {
         case Opcode::S_MOV_B32:
@@ -115,6 +145,9 @@ void Translate(IR::Block* block, Stage stage, std::span<const GcnInst> inst_list
             translator.V_MUL_F32(inst);
             break;
         case Opcode::S_SWAPPC_B64:
+            ASSERT(info.stage == Stage::Vertex);
+            translator.EmitFetch(inst);
+            break;
         case Opcode::S_WAITCNT:
             break; // Ignore for now.
         case Opcode::S_BUFFER_LOAD_DWORDX16:

src/shader_recompiler/frontend/translate/translate.h

@@ -7,9 +7,10 @@
 #include "shader_recompiler/frontend/instruction.h"
 #include "shader_recompiler/ir/basic_block.h"
 #include "shader_recompiler/ir/ir_emitter.h"
+#include "shader_recompiler/runtime_info.h"
 
 namespace Shader {
-enum class Stage : u32;
+struct Info;
 }
 
 namespace Shader::Gcn {
@@ -25,7 +26,9 @@ enum class ConditionOp : u32 {
 
 class Translator {
 public:
-    explicit Translator(IR::Block* block_, Stage stage);
+    explicit Translator(IR::Block* block_, Info& info);
+
+    void EmitFetch(const GcnInst& inst);
 
     // Scalar ALU
     void S_MOV(const GcnInst& inst);
@@ -66,8 +69,9 @@ private:
 private:
     IR::Block* block;
     IR::IREmitter ir;
+    Info& info;
 };
 
-void Translate(IR::Block* block, Stage stage, std::span<const GcnInst> inst_list);
+void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info);
 
 } // namespace Shader::Gcn

src/shader_recompiler/frontend/translate/vector_alu.cpp

@@ -20,9 +20,8 @@ void Translator::V_MAC_F32(const GcnInst& inst) {
 
 void Translator::V_CVT_PKRTZ_F16_F32(const GcnInst& inst) {
     const IR::VectorReg dst_reg{inst.dst[0].code};
-    const IR::Value vec_f32 = ir.CompositeConstruct(ir.FPConvert(16, GetSrc(inst.src[0])),
-                                                    ir.FPConvert(16, GetSrc(inst.src[1])));
-    ir.SetVectorReg(dst_reg, ir.PackFloat2x16(vec_f32));
+    const IR::Value vec_f32 = ir.CompositeConstruct(GetSrc(inst.src[0]), GetSrc(inst.src[1]));
+    ir.SetVectorReg(dst_reg, ir.PackHalf2x16(vec_f32));
 }
 
 void Translator::V_MUL_F32(const GcnInst& inst) {

src/shader_recompiler/frontend/translate/vector_interpolation.cpp

@@ -7,7 +7,9 @@ namespace Shader::Gcn {
 
 void Translator::V_INTERP_P2_F32(const GcnInst& inst) {
     const IR::VectorReg dst_reg{inst.dst[0].code};
-    const IR::Attribute attrib{IR::Attribute::Param0 + inst.control.vintrp.attr};
+    auto& attr = info.ps_inputs.at(inst.control.vintrp.attr);
+    attr.semantic = inst.control.vintrp.attr;
+    const IR::Attribute attrib{IR::Attribute::Param0 + attr.param_index};
     ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
 }