mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-06-14 22:53:15 +00:00
Image binding and texture cache interface refactor (1/2) (#1481)
* video_core: texture_cache: interface refactor and better overlap handling * resources binding moved into vk_rasterizer * remove `virtual` flag leftover
This commit is contained in:
psucien
GitHub
parent
16e1d679dc
commit
3d95ad0e3a
19 changed files with 911 additions and 679 deletions
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@ -15,8 +15,10 @@ ComputePipeline::ComputePipeline(const Instance& instance_, Scheduler& scheduler
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DescriptorHeap& desc_heap_, vk::PipelineCache pipeline_cache,
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u64 compute_key_, const Shader::Info& info_,
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vk::ShaderModule module)
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: Pipeline{instance_, scheduler_, desc_heap_, pipeline_cache}, compute_key{compute_key_},
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info{&info_} {
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: Pipeline{instance_, scheduler_, desc_heap_, pipeline_cache, true}, compute_key{compute_key_} {
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auto& info = stages[int(Shader::Stage::Compute)];
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info = &info_;
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const vk::PipelineShaderStageCreateInfo shader_ci = {
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.stage = vk::ShaderStageFlagBits::eCompute,
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.module = module,
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@ -118,90 +120,4 @@ ComputePipeline::ComputePipeline(const Instance& instance_, Scheduler& scheduler
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ComputePipeline::~ComputePipeline() = default;
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bool ComputePipeline::BindResources(VideoCore::BufferCache& buffer_cache,
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VideoCore::TextureCache& texture_cache) const {
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// Bind resource buffers and textures.
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boost::container::small_vector<vk::WriteDescriptorSet, 16> set_writes;
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BufferBarriers buffer_barriers;
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Shader::PushData push_data{};
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Shader::Backend::Bindings binding{};
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info->PushUd(binding, push_data);
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buffer_infos.clear();
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buffer_views.clear();
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image_infos.clear();
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// Most of the time when a metadata is updated with a shader it gets cleared. It means
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// we can skip the whole dispatch and update the tracked state instead. Also, it is not
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// intended to be consumed and in such rare cases (e.g. HTile introspection, CRAA) we
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// will need its full emulation anyways. For cases of metadata read a warning will be logged.
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const auto IsMetaUpdate = [&](const auto& desc) {
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const VAddr address = desc.GetSharp(*info).base_address;
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if (desc.is_written) {
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if (texture_cache.TouchMeta(address, true)) {
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LOG_TRACE(Render_Vulkan, "Metadata update skipped");
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return true;
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}
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} else {
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if (texture_cache.IsMeta(address)) {
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LOG_WARNING(Render_Vulkan, "Unexpected metadata read by a CS shader (buffer)");
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}
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}
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return false;
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};
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for (const auto& desc : info->buffers) {
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if (desc.is_gds_buffer) {
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continue;
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}
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if (IsMetaUpdate(desc)) {
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return false;
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}
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}
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for (const auto& desc : info->texture_buffers) {
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if (IsMetaUpdate(desc)) {
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return false;
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}
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}
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BindBuffers(buffer_cache, texture_cache, *info, binding, push_data, set_writes,
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buffer_barriers);
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BindTextures(texture_cache, *info, binding, set_writes);
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if (set_writes.empty()) {
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return false;
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}
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const auto cmdbuf = scheduler.CommandBuffer();
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if (!buffer_barriers.empty()) {
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const auto dependencies = vk::DependencyInfo{
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.dependencyFlags = vk::DependencyFlagBits::eByRegion,
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.bufferMemoryBarrierCount = u32(buffer_barriers.size()),
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.pBufferMemoryBarriers = buffer_barriers.data(),
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};
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scheduler.EndRendering();
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cmdbuf.pipelineBarrier2(dependencies);
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}
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cmdbuf.pushConstants(*pipeline_layout, vk::ShaderStageFlagBits::eCompute, 0u, sizeof(push_data),
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&push_data);
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// Bind descriptor set.
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if (uses_push_descriptors) {
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cmdbuf.pushDescriptorSetKHR(vk::PipelineBindPoint::eCompute, *pipeline_layout, 0,
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set_writes);
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return true;
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}
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const auto desc_set = desc_heap.Commit(*desc_layout);
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for (auto& set_write : set_writes) {
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set_write.dstSet = desc_set;
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}
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instance.GetDevice().updateDescriptorSets(set_writes, {});
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cmdbuf.bindDescriptorSets(vk::PipelineBindPoint::eCompute, *pipeline_layout, 0, desc_set, {});
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return true;
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}
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} // namespace Vulkan
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@ -24,13 +24,8 @@ public:
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vk::ShaderModule module);
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~ComputePipeline();
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bool BindResources(VideoCore::BufferCache& buffer_cache,
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VideoCore::TextureCache& texture_cache) const;
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private:
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u64 compute_key;
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const Shader::Info* info;
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bool uses_push_descriptors{};
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};
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} // namespace Vulkan
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@ -16,10 +16,6 @@
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namespace Vulkan {
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static constexpr auto gp_stage_flags = vk::ShaderStageFlagBits::eVertex |
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vk::ShaderStageFlagBits::eGeometry |
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vk::ShaderStageFlagBits::eFragment;
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GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& scheduler_,
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DescriptorHeap& desc_heap_, const GraphicsPipelineKey& key_,
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vk::PipelineCache pipeline_cache,
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@ -389,67 +385,4 @@ void GraphicsPipeline::BuildDescSetLayout() {
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desc_layout = std::move(layout);
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}
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void GraphicsPipeline::BindResources(const Liverpool::Regs& regs,
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VideoCore::BufferCache& buffer_cache,
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VideoCore::TextureCache& texture_cache) const {
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// Bind resource buffers and textures.
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boost::container::small_vector<vk::WriteDescriptorSet, 16> set_writes;
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BufferBarriers buffer_barriers;
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Shader::PushData push_data{};
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Shader::Backend::Bindings binding{};
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buffer_infos.clear();
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buffer_views.clear();
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image_infos.clear();
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for (const auto* stage : stages) {
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if (!stage) {
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continue;
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}
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if (stage->uses_step_rates) {
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push_data.step0 = regs.vgt_instance_step_rate_0;
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push_data.step1 = regs.vgt_instance_step_rate_1;
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}
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stage->PushUd(binding, push_data);
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BindBuffers(buffer_cache, texture_cache, *stage, binding, push_data, set_writes,
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buffer_barriers);
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BindTextures(texture_cache, *stage, binding, set_writes);
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}
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const auto cmdbuf = scheduler.CommandBuffer();
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SCOPE_EXIT {
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cmdbuf.pushConstants(*pipeline_layout, gp_stage_flags, 0U, sizeof(push_data), &push_data);
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cmdbuf.bindPipeline(vk::PipelineBindPoint::eGraphics, Handle());
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};
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if (set_writes.empty()) {
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return;
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}
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if (!buffer_barriers.empty()) {
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const auto dependencies = vk::DependencyInfo{
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.dependencyFlags = vk::DependencyFlagBits::eByRegion,
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.bufferMemoryBarrierCount = u32(buffer_barriers.size()),
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.pBufferMemoryBarriers = buffer_barriers.data(),
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};
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scheduler.EndRendering();
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cmdbuf.pipelineBarrier2(dependencies);
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}
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// Bind descriptor set.
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if (uses_push_descriptors) {
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cmdbuf.pushDescriptorSetKHR(vk::PipelineBindPoint::eGraphics, *pipeline_layout, 0,
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set_writes);
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return;
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}
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const auto desc_set = desc_heap.Commit(*desc_layout);
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for (auto& set_write : set_writes) {
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set_write.dstSet = desc_set;
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}
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instance.GetDevice().updateDescriptorSets(set_writes, {});
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cmdbuf.bindDescriptorSets(vk::PipelineBindPoint::eGraphics, *pipeline_layout, 0, desc_set, {});
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}
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} // namespace Vulkan
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@ -2,6 +2,7 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <xxhash.h>
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#include "common/types.h"
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#include "video_core/renderer_vulkan/liverpool_to_vk.h"
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#include "video_core/renderer_vulkan/vk_common.h"
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@ -14,8 +15,8 @@ class TextureCache;
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namespace Vulkan {
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static constexpr u32 MaxVertexBufferCount = 32;
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static constexpr u32 MaxShaderStages = 5;
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static constexpr u32 MaxVertexBufferCount = 32;
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class Instance;
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class Scheduler;
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@ -61,13 +62,6 @@ public:
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std::span<const vk::ShaderModule> modules);
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~GraphicsPipeline();
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void BindResources(const Liverpool::Regs& regs, VideoCore::BufferCache& buffer_cache,
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VideoCore::TextureCache& texture_cache) const;
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const Shader::Info& GetStage(Shader::Stage stage) const noexcept {
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return *stages[u32(stage)];
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}
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bool IsEmbeddedVs() const noexcept {
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static constexpr size_t EmbeddedVsHash = 0x9b2da5cf47f8c29f;
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return key.stage_hashes[u32(Shader::Stage::Vertex)] == EmbeddedVsHash;
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@ -99,9 +93,7 @@ private:
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void BuildDescSetLayout();
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private:
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std::array<const Shader::Info*, MaxShaderStages> stages{};
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GraphicsPipelineKey key;
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bool uses_push_descriptors{};
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};
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} // namespace Vulkan
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@ -38,8 +38,6 @@ struct Program {
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};
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class PipelineCache {
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static constexpr size_t MaxShaderStages = 5;
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public:
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explicit PipelineCache(const Instance& instance, Scheduler& scheduler,
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AmdGpu::Liverpool* liverpool);
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@ -12,230 +12,47 @@
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namespace Vulkan {
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boost::container::static_vector<vk::DescriptorImageInfo, 32> Pipeline::image_infos;
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boost::container::static_vector<vk::BufferView, 8> Pipeline::buffer_views;
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boost::container::static_vector<vk::DescriptorBufferInfo, 32> Pipeline::buffer_infos;
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Pipeline::Pipeline(const Instance& instance_, Scheduler& scheduler_, DescriptorHeap& desc_heap_,
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vk::PipelineCache pipeline_cache)
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: instance{instance_}, scheduler{scheduler_}, desc_heap{desc_heap_} {}
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vk::PipelineCache pipeline_cache, bool is_compute_ /*= false*/)
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: instance{instance_}, scheduler{scheduler_}, desc_heap{desc_heap_}, is_compute{is_compute_} {}
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Pipeline::~Pipeline() = default;
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void Pipeline::BindBuffers(VideoCore::BufferCache& buffer_cache,
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VideoCore::TextureCache& texture_cache, const Shader::Info& stage,
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Shader::Backend::Bindings& binding, Shader::PushData& push_data,
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DescriptorWrites& set_writes, BufferBarriers& buffer_barriers) const {
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using BufferBindingInfo = std::pair<VideoCore::BufferId, AmdGpu::Buffer>;
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static boost::container::static_vector<BufferBindingInfo, 32> buffer_bindings;
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void Pipeline::BindResources(DescriptorWrites& set_writes, const BufferBarriers& buffer_barriers,
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const Shader::PushData& push_data) const {
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const auto cmdbuf = scheduler.CommandBuffer();
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const auto bind_point =
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IsCompute() ? vk::PipelineBindPoint::eCompute : vk::PipelineBindPoint::eGraphics;
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buffer_bindings.clear();
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for (const auto& desc : stage.buffers) {
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const auto vsharp = desc.GetSharp(stage);
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if (!desc.is_gds_buffer && vsharp.base_address != 0 && vsharp.GetSize() > 0) {
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const auto buffer_id = buffer_cache.FindBuffer(vsharp.base_address, vsharp.GetSize());
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buffer_bindings.emplace_back(buffer_id, vsharp);
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} else {
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buffer_bindings.emplace_back(VideoCore::BufferId{}, vsharp);
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}
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if (!buffer_barriers.empty()) {
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const auto dependencies = vk::DependencyInfo{
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.dependencyFlags = vk::DependencyFlagBits::eByRegion,
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.bufferMemoryBarrierCount = u32(buffer_barriers.size()),
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.pBufferMemoryBarriers = buffer_barriers.data(),
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};
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scheduler.EndRendering();
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cmdbuf.pipelineBarrier2(dependencies);
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}
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using TexBufferBindingInfo = std::pair<VideoCore::BufferId, AmdGpu::Buffer>;
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static boost::container::static_vector<TexBufferBindingInfo, 32> texbuffer_bindings;
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const auto stage_flags = IsCompute() ? vk::ShaderStageFlagBits::eCompute : gp_stage_flags;
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cmdbuf.pushConstants(*pipeline_layout, stage_flags, 0u, sizeof(push_data), &push_data);
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texbuffer_bindings.clear();
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for (const auto& desc : stage.texture_buffers) {
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const auto vsharp = desc.GetSharp(stage);
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if (vsharp.base_address != 0 && vsharp.GetSize() > 0 &&
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vsharp.GetDataFmt() != AmdGpu::DataFormat::FormatInvalid) {
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const auto buffer_id = buffer_cache.FindBuffer(vsharp.base_address, vsharp.GetSize());
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texbuffer_bindings.emplace_back(buffer_id, vsharp);
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} else {
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texbuffer_bindings.emplace_back(VideoCore::BufferId{}, vsharp);
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}
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// Bind descriptor set.
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if (set_writes.empty()) {
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return;
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}
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// Bind the flattened user data buffer as a UBO so it's accessible to the shader
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if (stage.has_readconst) {
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const auto [vk_buffer, offset] = buffer_cache.ObtainHostUBO(stage.flattened_ud_buf);
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buffer_infos.emplace_back(vk_buffer->Handle(), offset,
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stage.flattened_ud_buf.size() * sizeof(u32));
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set_writes.push_back({
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.dstSet = VK_NULL_HANDLE,
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.dstBinding = binding.unified++,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = vk::DescriptorType::eUniformBuffer,
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.pBufferInfo = &buffer_infos.back(),
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});
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++binding.buffer;
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if (uses_push_descriptors) {
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cmdbuf.pushDescriptorSetKHR(bind_point, *pipeline_layout, 0, set_writes);
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return;
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}
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// Second pass to re-bind buffers that were updated after binding
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for (u32 i = 0; i < buffer_bindings.size(); i++) {
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const auto& [buffer_id, vsharp] = buffer_bindings[i];
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const auto& desc = stage.buffers[i];
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const bool is_storage = desc.IsStorage(vsharp);
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if (!buffer_id) {
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if (desc.is_gds_buffer) {
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const auto* gds_buf = buffer_cache.GetGdsBuffer();
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buffer_infos.emplace_back(gds_buf->Handle(), 0, gds_buf->SizeBytes());
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} else if (instance.IsNullDescriptorSupported()) {
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buffer_infos.emplace_back(VK_NULL_HANDLE, 0, VK_WHOLE_SIZE);
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} else {
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auto& null_buffer = buffer_cache.GetBuffer(VideoCore::NULL_BUFFER_ID);
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buffer_infos.emplace_back(null_buffer.Handle(), 0, VK_WHOLE_SIZE);
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}
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} else {
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const auto [vk_buffer, offset] = buffer_cache.ObtainBuffer(
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vsharp.base_address, vsharp.GetSize(), desc.is_written, false, buffer_id);
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const u32 alignment =
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is_storage ? instance.StorageMinAlignment() : instance.UniformMinAlignment();
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const u32 offset_aligned = Common::AlignDown(offset, alignment);
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const u32 adjust = offset - offset_aligned;
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ASSERT(adjust % 4 == 0);
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push_data.AddOffset(binding.buffer, adjust);
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buffer_infos.emplace_back(vk_buffer->Handle(), offset_aligned,
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vsharp.GetSize() + adjust);
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}
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set_writes.push_back({
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.dstSet = VK_NULL_HANDLE,
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.dstBinding = binding.unified++,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = is_storage ? vk::DescriptorType::eStorageBuffer
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: vk::DescriptorType::eUniformBuffer,
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.pBufferInfo = &buffer_infos.back(),
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});
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++binding.buffer;
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}
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const auto null_buffer_view =
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instance.IsNullDescriptorSupported() ? VK_NULL_HANDLE : buffer_cache.NullBufferView();
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for (u32 i = 0; i < texbuffer_bindings.size(); i++) {
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const auto& [buffer_id, vsharp] = texbuffer_bindings[i];
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const auto& desc = stage.texture_buffers[i];
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vk::BufferView& buffer_view = buffer_views.emplace_back(null_buffer_view);
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if (buffer_id) {
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const u32 alignment = instance.TexelBufferMinAlignment();
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const auto [vk_buffer, offset] = buffer_cache.ObtainBuffer(
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vsharp.base_address, vsharp.GetSize(), desc.is_written, true, buffer_id);
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const u32 fmt_stride = AmdGpu::NumBits(vsharp.GetDataFmt()) >> 3;
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ASSERT_MSG(fmt_stride == vsharp.GetStride(),
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"Texel buffer stride must match format stride");
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const u32 offset_aligned = Common::AlignDown(offset, alignment);
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const u32 adjust = offset - offset_aligned;
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ASSERT(adjust % fmt_stride == 0);
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push_data.AddOffset(binding.buffer, adjust / fmt_stride);
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buffer_view =
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vk_buffer->View(offset_aligned, vsharp.GetSize() + adjust, desc.is_written,
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vsharp.GetDataFmt(), vsharp.GetNumberFmt());
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if (auto barrier =
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vk_buffer->GetBarrier(desc.is_written ? vk::AccessFlagBits2::eShaderWrite
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: vk::AccessFlagBits2::eShaderRead,
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vk::PipelineStageFlagBits2::eComputeShader)) {
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buffer_barriers.emplace_back(*barrier);
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}
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if (desc.is_written) {
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texture_cache.InvalidateMemoryFromGPU(vsharp.base_address, vsharp.GetSize());
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}
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}
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set_writes.push_back({
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.dstSet = VK_NULL_HANDLE,
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.dstBinding = binding.unified++,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = desc.is_written ? vk::DescriptorType::eStorageTexelBuffer
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: vk::DescriptorType::eUniformTexelBuffer,
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.pTexelBufferView = &buffer_view,
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});
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++binding.buffer;
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}
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}
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|
||||
void Pipeline::BindTextures(VideoCore::TextureCache& texture_cache, const Shader::Info& stage,
|
||||
Shader::Backend::Bindings& binding,
|
||||
DescriptorWrites& set_writes) const {
|
||||
|
||||
using ImageBindingInfo = std::tuple<VideoCore::ImageId, AmdGpu::Image, Shader::ImageResource>;
|
||||
static boost::container::static_vector<ImageBindingInfo, 32> image_bindings;
|
||||
|
||||
image_bindings.clear();
|
||||
|
||||
for (const auto& image_desc : stage.images) {
|
||||
const auto tsharp = image_desc.GetSharp(stage);
|
||||
if (tsharp.GetDataFmt() != AmdGpu::DataFormat::FormatInvalid) {
|
||||
VideoCore::ImageInfo image_info{tsharp, image_desc};
|
||||
const auto image_id = texture_cache.FindImage(image_info);
|
||||
auto& image = texture_cache.GetImage(image_id);
|
||||
image.flags |= VideoCore::ImageFlagBits::Bound;
|
||||
image_bindings.emplace_back(image_id, tsharp, image_desc);
|
||||
} else {
|
||||
image_bindings.emplace_back(VideoCore::ImageId{}, tsharp, image_desc);
|
||||
}
|
||||
|
||||
if (texture_cache.IsMeta(tsharp.Address())) {
|
||||
LOG_WARNING(Render_Vulkan, "Unexpected metadata read by a PS shader (texture)");
|
||||
}
|
||||
}
|
||||
|
||||
// Second pass to re-bind images that were updated after binding
|
||||
for (auto [image_id, tsharp, desc] : image_bindings) {
|
||||
if (!image_id) {
|
||||
if (instance.IsNullDescriptorSupported()) {
|
||||
image_infos.emplace_back(VK_NULL_HANDLE, VK_NULL_HANDLE, vk::ImageLayout::eGeneral);
|
||||
} else {
|
||||
auto& null_image = texture_cache.GetImageView(VideoCore::NULL_IMAGE_VIEW_ID);
|
||||
image_infos.emplace_back(VK_NULL_HANDLE, *null_image.image_view,
|
||||
vk::ImageLayout::eGeneral);
|
||||
}
|
||||
} else {
|
||||
auto& image = texture_cache.GetImage(image_id);
|
||||
if (True(image.flags & VideoCore::ImageFlagBits::NeedsRebind)) {
|
||||
image_id = texture_cache.FindImage(image.info);
|
||||
}
|
||||
VideoCore::ImageViewInfo view_info{tsharp, desc};
|
||||
auto& image_view = texture_cache.FindTexture(image_id, view_info);
|
||||
image_infos.emplace_back(VK_NULL_HANDLE, *image_view.image_view,
|
||||
texture_cache.GetImage(image_id).last_state.layout);
|
||||
image.flags &=
|
||||
~(VideoCore::ImageFlagBits::NeedsRebind | VideoCore::ImageFlagBits::Bound);
|
||||
}
|
||||
|
||||
set_writes.push_back({
|
||||
.dstSet = VK_NULL_HANDLE,
|
||||
.dstBinding = binding.unified++,
|
||||
.dstArrayElement = 0,
|
||||
.descriptorCount = 1,
|
||||
.descriptorType = desc.is_storage ? vk::DescriptorType::eStorageImage
|
||||
: vk::DescriptorType::eSampledImage,
|
||||
.pImageInfo = &image_infos.back(),
|
||||
});
|
||||
}
|
||||
|
||||
for (const auto& sampler : stage.samplers) {
|
||||
auto ssharp = sampler.GetSharp(stage);
|
||||
if (sampler.disable_aniso) {
|
||||
const auto& tsharp = stage.images[sampler.associated_image].GetSharp(stage);
|
||||
if (tsharp.base_level == 0 && tsharp.last_level == 0) {
|
||||
ssharp.max_aniso.Assign(AmdGpu::AnisoRatio::One);
|
||||
}
|
||||
}
|
||||
const auto vk_sampler = texture_cache.GetSampler(ssharp);
|
||||
image_infos.emplace_back(vk_sampler, VK_NULL_HANDLE, vk::ImageLayout::eGeneral);
|
||||
set_writes.push_back({
|
||||
.dstSet = VK_NULL_HANDLE,
|
||||
.dstBinding = binding.unified++,
|
||||
.dstArrayElement = 0,
|
||||
.descriptorCount = 1,
|
||||
.descriptorType = vk::DescriptorType::eSampler,
|
||||
.pImageInfo = &image_infos.back(),
|
||||
});
|
||||
const auto desc_set = desc_heap.Commit(*desc_layout);
|
||||
for (auto& set_write : set_writes) {
|
||||
set_write.dstSet = desc_set;
|
||||
}
|
||||
instance.GetDevice().updateDescriptorSets(set_writes, {});
|
||||
cmdbuf.bindDescriptorSets(bind_point, *pipeline_layout, 0, desc_set, {});
|
||||
}
|
||||
|
||||
} // namespace Vulkan
|
||||
|
|
|
|||
|
|
@ -6,14 +6,18 @@
|
|||
#include "shader_recompiler/backend/bindings.h"
|
||||
#include "shader_recompiler/info.h"
|
||||
#include "video_core/renderer_vulkan/vk_common.h"
|
||||
#include "video_core/texture_cache/texture_cache.h"
|
||||
|
||||
namespace VideoCore {
|
||||
class BufferCache;
|
||||
class TextureCache;
|
||||
} // namespace VideoCore
|
||||
|
||||
namespace Vulkan {
|
||||
|
||||
static constexpr auto gp_stage_flags = vk::ShaderStageFlagBits::eVertex |
|
||||
vk::ShaderStageFlagBits::eGeometry |
|
||||
vk::ShaderStageFlagBits::eFragment;
|
||||
|
||||
class Instance;
|
||||
class Scheduler;
|
||||
class DescriptorHeap;
|
||||
|
|
@ -21,7 +25,7 @@ class DescriptorHeap;
|
|||
class Pipeline {
|
||||
public:
|
||||
Pipeline(const Instance& instance, Scheduler& scheduler, DescriptorHeap& desc_heap,
|
||||
vk::PipelineCache pipeline_cache);
|
||||
vk::PipelineCache pipeline_cache, bool is_compute = false);
|
||||
virtual ~Pipeline();
|
||||
|
||||
vk::Pipeline Handle() const noexcept {
|
||||
|
|
@ -32,16 +36,27 @@ public:
|
|||
return *pipeline_layout;
|
||||
}
|
||||
|
||||
auto GetStages() const {
|
||||
if (is_compute) {
|
||||
return std::span{stages.cend() - 1, stages.cend()};
|
||||
} else {
|
||||
return std::span{stages.cbegin(), stages.cend() - 1};
|
||||
}
|
||||
}
|
||||
|
||||
const Shader::Info& GetStage(Shader::Stage stage) const noexcept {
|
||||
return *stages[u32(stage)];
|
||||
}
|
||||
|
||||
bool IsCompute() const {
|
||||
return is_compute;
|
||||
}
|
||||
|
||||
using DescriptorWrites = boost::container::small_vector<vk::WriteDescriptorSet, 16>;
|
||||
using BufferBarriers = boost::container::small_vector<vk::BufferMemoryBarrier2, 16>;
|
||||
|
||||
void BindBuffers(VideoCore::BufferCache& buffer_cache, VideoCore::TextureCache& texture_cache,
|
||||
const Shader::Info& stage, Shader::Backend::Bindings& binding,
|
||||
Shader::PushData& push_data, DescriptorWrites& set_writes,
|
||||
BufferBarriers& buffer_barriers) const;
|
||||
|
||||
void BindTextures(VideoCore::TextureCache& texture_cache, const Shader::Info& stage,
|
||||
Shader::Backend::Bindings& binding, DescriptorWrites& set_writes) const;
|
||||
void BindResources(DescriptorWrites& set_writes, const BufferBarriers& buffer_barriers,
|
||||
const Shader::PushData& push_data) const;
|
||||
|
||||
protected:
|
||||
const Instance& instance;
|
||||
|
|
@ -50,9 +65,9 @@ protected:
|
|||
vk::UniquePipeline pipeline;
|
||||
vk::UniquePipelineLayout pipeline_layout;
|
||||
vk::UniqueDescriptorSetLayout desc_layout;
|
||||
static boost::container::static_vector<vk::DescriptorImageInfo, 32> image_infos;
|
||||
static boost::container::static_vector<vk::BufferView, 8> buffer_views;
|
||||
static boost::container::static_vector<vk::DescriptorBufferInfo, 32> buffer_infos;
|
||||
std::array<const Shader::Info*, Shader::MaxStageTypes> stages{};
|
||||
bool uses_push_descriptors{};
|
||||
const bool is_compute;
|
||||
};
|
||||
|
||||
} // namespace Vulkan
|
||||
|
|
|
|||
|
|
@ -55,8 +55,8 @@ public:
|
|||
|
||||
Frame* PrepareFrame(const Libraries::VideoOut::BufferAttributeGroup& attribute,
|
||||
VAddr cpu_address, bool is_eop) {
|
||||
const auto info = VideoCore::ImageInfo{attribute, cpu_address};
|
||||
const auto image_id = texture_cache.FindImage(info);
|
||||
auto desc = VideoCore::TextureCache::VideoOutDesc{attribute, cpu_address};
|
||||
const auto image_id = texture_cache.FindImage(desc);
|
||||
texture_cache.UpdateImage(image_id, is_eop ? nullptr : &flip_scheduler);
|
||||
return PrepareFrameInternal(image_id, is_eop);
|
||||
}
|
||||
|
|
@ -68,9 +68,11 @@ public:
|
|||
VideoCore::Image& RegisterVideoOutSurface(
|
||||
const Libraries::VideoOut::BufferAttributeGroup& attribute, VAddr cpu_address) {
|
||||
vo_buffers_addr.emplace_back(cpu_address);
|
||||
const auto info = VideoCore::ImageInfo{attribute, cpu_address};
|
||||
const auto image_id = texture_cache.FindImage(info);
|
||||
return texture_cache.GetImage(image_id);
|
||||
auto desc = VideoCore::TextureCache::VideoOutDesc{attribute, cpu_address};
|
||||
const auto image_id = texture_cache.FindImage(desc);
|
||||
auto& image = texture_cache.GetImage(image_id);
|
||||
image.usage.vo_surface = 1u;
|
||||
return image;
|
||||
}
|
||||
|
||||
bool IsVideoOutSurface(const AmdGpu::Liverpool::ColorBuffer& color_buffer) {
|
||||
|
|
|
|||
|
|
@ -75,6 +75,105 @@ bool Rasterizer::FilterDraw() {
|
|||
return true;
|
||||
}
|
||||
|
||||
RenderState Rasterizer::PrepareRenderState(u32 mrt_mask) {
|
||||
// Prefetch color and depth buffers to let texture cache handle possible overlaps with bound
|
||||
// textures (e.g. mipgen)
|
||||
RenderState state;
|
||||
|
||||
cb_descs.clear();
|
||||
db_desc.reset();
|
||||
|
||||
const auto& regs = liverpool->regs;
|
||||
|
||||
if (regs.color_control.degamma_enable) {
|
||||
LOG_WARNING(Render_Vulkan, "Color buffers require gamma correction");
|
||||
}
|
||||
|
||||
for (auto col_buf_id = 0u; col_buf_id < Liverpool::NumColorBuffers; ++col_buf_id) {
|
||||
const auto& col_buf = regs.color_buffers[col_buf_id];
|
||||
if (!col_buf) {
|
||||
continue;
|
||||
}
|
||||
|
||||
// If the color buffer is still bound but rendering to it is disabled by the target
|
||||
// mask, we need to prevent the render area from being affected by unbound render target
|
||||
// extents.
|
||||
if (!regs.color_target_mask.GetMask(col_buf_id)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
// Skip stale color buffers if shader doesn't output to them. Otherwise it will perform
|
||||
// an unnecessary transition and may result in state conflict if the resource is already
|
||||
// bound for reading.
|
||||
if ((mrt_mask & (1 << col_buf_id)) == 0) {
|
||||
continue;
|
||||
}
|
||||
|
||||
const bool is_clear = texture_cache.IsMetaCleared(col_buf.CmaskAddress());
|
||||
texture_cache.TouchMeta(col_buf.CmaskAddress(), false);
|
||||
|
||||
const auto& hint = liverpool->last_cb_extent[col_buf_id];
|
||||
auto& [image_id, desc] = cb_descs.emplace_back(std::piecewise_construct, std::tuple{},
|
||||
std::tuple{col_buf, hint});
|
||||
const auto& image_view = texture_cache.FindRenderTarget(desc);
|
||||
image_id = bound_images.emplace_back(image_view.image_id);
|
||||
auto& image = texture_cache.GetImage(image_id);
|
||||
image.binding.is_target = 1u;
|
||||
|
||||
const auto mip = image_view.info.range.base.level;
|
||||
state.width = std::min<u32>(state.width, std::max(image.info.size.width >> mip, 1u));
|
||||
state.height = std::min<u32>(state.height, std::max(image.info.size.height >> mip, 1u));
|
||||
state.color_images[state.num_color_attachments] = image.image;
|
||||
state.color_attachments[state.num_color_attachments++] = {
|
||||
.imageView = *image_view.image_view,
|
||||
.imageLayout = vk::ImageLayout::eUndefined,
|
||||
.loadOp = is_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
|
||||
.storeOp = vk::AttachmentStoreOp::eStore,
|
||||
.clearValue =
|
||||
is_clear ? LiverpoolToVK::ColorBufferClearValue(col_buf) : vk::ClearValue{},
|
||||
};
|
||||
}
|
||||
|
||||
using ZFormat = AmdGpu::Liverpool::DepthBuffer::ZFormat;
|
||||
using StencilFormat = AmdGpu::Liverpool::DepthBuffer::StencilFormat;
|
||||
if (regs.depth_buffer.Address() != 0 &&
|
||||
((regs.depth_control.depth_enable && regs.depth_buffer.z_info.format != ZFormat::Invalid) ||
|
||||
(regs.depth_control.stencil_enable &&
|
||||
regs.depth_buffer.stencil_info.format != StencilFormat::Invalid))) {
|
||||
const auto htile_address = regs.depth_htile_data_base.GetAddress();
|
||||
const bool is_clear = regs.depth_render_control.depth_clear_enable ||
|
||||
texture_cache.IsMetaCleared(htile_address);
|
||||
const auto& hint = liverpool->last_db_extent;
|
||||
auto& [image_id, desc] =
|
||||
db_desc.emplace(std::piecewise_construct, std::tuple{},
|
||||
std::tuple{regs.depth_buffer, regs.depth_view, regs.depth_control,
|
||||
htile_address, hint});
|
||||
const auto& image_view = texture_cache.FindDepthTarget(desc);
|
||||
image_id = bound_images.emplace_back(image_view.image_id);
|
||||
auto& image = texture_cache.GetImage(image_id);
|
||||
image.binding.is_target = 1u;
|
||||
|
||||
state.width = std::min<u32>(state.width, image.info.size.width);
|
||||
state.height = std::min<u32>(state.height, image.info.size.height);
|
||||
state.depth_image = image.image;
|
||||
state.depth_attachment = {
|
||||
.imageView = *image_view.image_view,
|
||||
.imageLayout = vk::ImageLayout::eUndefined,
|
||||
.loadOp = is_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
|
||||
.storeOp = vk::AttachmentStoreOp::eStore,
|
||||
.clearValue = vk::ClearValue{.depthStencil = {.depth = regs.depth_clear,
|
||||
.stencil = regs.stencil_clear}},
|
||||
};
|
||||
texture_cache.TouchMeta(htile_address, false);
|
||||
state.has_depth =
|
||||
regs.depth_buffer.z_info.format != AmdGpu::Liverpool::DepthBuffer::ZFormat::Invalid;
|
||||
state.has_stencil = regs.depth_buffer.stencil_info.format !=
|
||||
AmdGpu::Liverpool::DepthBuffer::StencilFormat::Invalid;
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
|
||||
RENDERER_TRACE;
|
||||
|
||||
|
|
@ -82,28 +181,30 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
|
|||
return;
|
||||
}
|
||||
|
||||
const auto cmdbuf = scheduler.CommandBuffer();
|
||||
const auto& regs = liverpool->regs;
|
||||
const GraphicsPipeline* pipeline = pipeline_cache.GetGraphicsPipeline();
|
||||
if (!pipeline) {
|
||||
return;
|
||||
}
|
||||
|
||||
try {
|
||||
pipeline->BindResources(regs, buffer_cache, texture_cache);
|
||||
} catch (...) {
|
||||
UNREACHABLE();
|
||||
auto state = PrepareRenderState(pipeline->GetMrtMask());
|
||||
|
||||
if (!BindResources(pipeline)) {
|
||||
return;
|
||||
}
|
||||
|
||||
const auto& vs_info = pipeline->GetStage(Shader::Stage::Vertex);
|
||||
buffer_cache.BindVertexBuffers(vs_info);
|
||||
const u32 num_indices = buffer_cache.BindIndexBuffer(is_indexed, index_offset);
|
||||
|
||||
BeginRendering(*pipeline);
|
||||
BeginRendering(*pipeline, state);
|
||||
UpdateDynamicState(*pipeline);
|
||||
|
||||
const auto [vertex_offset, instance_offset] = vs_info.GetDrawOffsets();
|
||||
|
||||
const auto cmdbuf = scheduler.CommandBuffer();
|
||||
cmdbuf.bindPipeline(vk::PipelineBindPoint::eGraphics, pipeline->Handle());
|
||||
|
||||
if (is_indexed) {
|
||||
cmdbuf.drawIndexed(num_indices, regs.num_instances.NumInstances(), 0, s32(vertex_offset),
|
||||
instance_offset);
|
||||
|
|
@ -113,6 +214,8 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
|
|||
cmdbuf.draw(num_vertices, regs.num_instances.NumInstances(), vertex_offset,
|
||||
instance_offset);
|
||||
}
|
||||
|
||||
ResetBindings();
|
||||
}
|
||||
|
||||
void Rasterizer::DrawIndirect(bool is_indexed, VAddr arg_address, u32 offset, u32 stride,
|
||||
|
|
@ -123,19 +226,19 @@ void Rasterizer::DrawIndirect(bool is_indexed, VAddr arg_address, u32 offset, u3
|
|||
return;
|
||||
}
|
||||
|
||||
const auto& regs = liverpool->regs;
|
||||
const GraphicsPipeline* pipeline = pipeline_cache.GetGraphicsPipeline();
|
||||
if (!pipeline) {
|
||||
return;
|
||||
}
|
||||
|
||||
auto state = PrepareRenderState(pipeline->GetMrtMask());
|
||||
|
||||
const auto& regs = liverpool->regs;
|
||||
ASSERT_MSG(regs.primitive_type != AmdGpu::PrimitiveType::RectList,
|
||||
"Unsupported primitive type for indirect draw");
|
||||
|
||||
try {
|
||||
pipeline->BindResources(regs, buffer_cache, texture_cache);
|
||||
} catch (...) {
|
||||
UNREACHABLE();
|
||||
if (!BindResources(pipeline)) {
|
||||
return;
|
||||
}
|
||||
|
||||
const auto& vs_info = pipeline->GetStage(Shader::Stage::Vertex);
|
||||
|
|
@ -151,13 +254,15 @@ void Rasterizer::DrawIndirect(bool is_indexed, VAddr arg_address, u32 offset, u3
|
|||
std::tie(count_buffer, count_base) = buffer_cache.ObtainBuffer(count_address, 4, false);
|
||||
}
|
||||
|
||||
BeginRendering(*pipeline);
|
||||
BeginRendering(*pipeline, state);
|
||||
UpdateDynamicState(*pipeline);
|
||||
|
||||
// We can safely ignore both SGPR UD indices and results of fetch shader parsing, as vertex and
|
||||
// instance offsets will be automatically applied by Vulkan from indirect args buffer.
|
||||
|
||||
const auto cmdbuf = scheduler.CommandBuffer();
|
||||
cmdbuf.bindPipeline(vk::PipelineBindPoint::eGraphics, pipeline->Handle());
|
||||
|
||||
if (is_indexed) {
|
||||
ASSERT(sizeof(VkDrawIndexedIndirectCommand) == stride);
|
||||
|
||||
|
|
@ -177,6 +282,8 @@ void Rasterizer::DrawIndirect(bool is_indexed, VAddr arg_address, u32 offset, u3
|
|||
cmdbuf.drawIndirect(buffer->Handle(), base, max_count, stride);
|
||||
}
|
||||
}
|
||||
|
||||
ResetBindings();
|
||||
}
|
||||
|
||||
void Rasterizer::DispatchDirect() {
|
||||
|
|
@ -189,18 +296,15 @@ void Rasterizer::DispatchDirect() {
|
|||
return;
|
||||
}
|
||||
|
||||
try {
|
||||
const auto has_resources = pipeline->BindResources(buffer_cache, texture_cache);
|
||||
if (!has_resources) {
|
||||
return;
|
||||
}
|
||||
} catch (...) {
|
||||
UNREACHABLE();
|
||||
if (!BindResources(pipeline)) {
|
||||
return;
|
||||
}
|
||||
|
||||
scheduler.EndRendering();
|
||||
cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, pipeline->Handle());
|
||||
cmdbuf.dispatch(cs_program.dim_x, cs_program.dim_y, cs_program.dim_z);
|
||||
|
||||
ResetBindings();
|
||||
}
|
||||
|
||||
void Rasterizer::DispatchIndirect(VAddr address, u32 offset, u32 size) {
|
||||
|
|
@ -213,19 +317,16 @@ void Rasterizer::DispatchIndirect(VAddr address, u32 offset, u32 size) {
|
|||
return;
|
||||
}
|
||||
|
||||
try {
|
||||
const auto has_resources = pipeline->BindResources(buffer_cache, texture_cache);
|
||||
if (!has_resources) {
|
||||
return;
|
||||
}
|
||||
} catch (...) {
|
||||
UNREACHABLE();
|
||||
if (!BindResources(pipeline)) {
|
||||
return;
|
||||
}
|
||||
|
||||
scheduler.EndRendering();
|
||||
cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, pipeline->Handle());
|
||||
const auto [buffer, base] = buffer_cache.ObtainBuffer(address + offset, size, false);
|
||||
cmdbuf.dispatchIndirect(buffer->Handle(), base);
|
||||
|
||||
ResetBindings();
|
||||
}
|
||||
|
||||
u64 Rasterizer::Flush() {
|
||||
|
|
@ -239,86 +340,386 @@ void Rasterizer::Finish() {
|
|||
scheduler.Finish();
|
||||
}
|
||||
|
||||
void Rasterizer::BeginRendering(const GraphicsPipeline& pipeline) {
|
||||
bool Rasterizer::BindResources(const Pipeline* pipeline) {
|
||||
buffer_infos.clear();
|
||||
buffer_views.clear();
|
||||
image_infos.clear();
|
||||
|
||||
const auto& regs = liverpool->regs;
|
||||
RenderState state;
|
||||
|
||||
if (regs.color_control.degamma_enable) {
|
||||
LOG_WARNING(Render_Vulkan, "Color buffers require gamma correction");
|
||||
}
|
||||
if (pipeline->IsCompute()) {
|
||||
const auto& info = pipeline->GetStage(Shader::Stage::Compute);
|
||||
|
||||
for (auto col_buf_id = 0u; col_buf_id < Liverpool::NumColorBuffers; ++col_buf_id) {
|
||||
const auto& col_buf = regs.color_buffers[col_buf_id];
|
||||
if (!col_buf) {
|
||||
continue;
|
||||
}
|
||||
|
||||
// If the color buffer is still bound but rendering to it is disabled by the target mask,
|
||||
// we need to prevent the render area from being affected by unbound render target extents.
|
||||
if (!regs.color_target_mask.GetMask(col_buf_id)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
// Skip stale color buffers if shader doesn't output to them. Otherwise it will perform
|
||||
// an unnecessary transition and may result in state conflict if the resource is already
|
||||
// bound for reading.
|
||||
if ((pipeline.GetMrtMask() & (1 << col_buf_id)) == 0) {
|
||||
continue;
|
||||
}
|
||||
|
||||
const auto& hint = liverpool->last_cb_extent[col_buf_id];
|
||||
VideoCore::ImageInfo image_info{col_buf, hint};
|
||||
VideoCore::ImageViewInfo view_info{col_buf};
|
||||
const auto& image_view = texture_cache.FindRenderTarget(image_info, view_info);
|
||||
const auto& image = texture_cache.GetImage(image_view.image_id);
|
||||
state.width = std::min<u32>(state.width, image.info.size.width);
|
||||
state.height = std::min<u32>(state.height, image.info.size.height);
|
||||
|
||||
const bool is_clear = texture_cache.IsMetaCleared(col_buf.CmaskAddress());
|
||||
state.color_images[state.num_color_attachments] = image.image;
|
||||
state.color_attachments[state.num_color_attachments++] = {
|
||||
.imageView = *image_view.image_view,
|
||||
.imageLayout = vk::ImageLayout::eColorAttachmentOptimal,
|
||||
.loadOp = is_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
|
||||
.storeOp = vk::AttachmentStoreOp::eStore,
|
||||
.clearValue =
|
||||
is_clear ? LiverpoolToVK::ColorBufferClearValue(col_buf) : vk::ClearValue{},
|
||||
// Most of the time when a metadata is updated with a shader it gets cleared. It means
|
||||
// we can skip the whole dispatch and update the tracked state instead. Also, it is not
|
||||
// intended to be consumed and in such rare cases (e.g. HTile introspection, CRAA) we
|
||||
// will need its full emulation anyways. For cases of metadata read a warning will be
|
||||
// logged.
|
||||
const auto IsMetaUpdate = [&](const auto& desc) {
|
||||
const VAddr address = desc.GetSharp(info).base_address;
|
||||
if (desc.is_written) {
|
||||
if (texture_cache.TouchMeta(address, true)) {
|
||||
LOG_TRACE(Render_Vulkan, "Metadata update skipped");
|
||||
return true;
|
||||
}
|
||||
} else {
|
||||
if (texture_cache.IsMeta(address)) {
|
||||
LOG_WARNING(Render_Vulkan, "Unexpected metadata read by a CS shader (buffer)");
|
||||
}
|
||||
}
|
||||
return false;
|
||||
};
|
||||
texture_cache.TouchMeta(col_buf.CmaskAddress(), false);
|
||||
|
||||
for (const auto& desc : info.buffers) {
|
||||
if (desc.is_gds_buffer) {
|
||||
continue;
|
||||
}
|
||||
if (IsMetaUpdate(desc)) {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
for (const auto& desc : info.texture_buffers) {
|
||||
if (IsMetaUpdate(desc)) {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
using ZFormat = AmdGpu::Liverpool::DepthBuffer::ZFormat;
|
||||
using StencilFormat = AmdGpu::Liverpool::DepthBuffer::StencilFormat;
|
||||
if (regs.depth_buffer.Address() != 0 &&
|
||||
((regs.depth_control.depth_enable && regs.depth_buffer.z_info.format != ZFormat::Invalid) ||
|
||||
(regs.depth_control.stencil_enable &&
|
||||
regs.depth_buffer.stencil_info.format != StencilFormat::Invalid))) {
|
||||
const auto htile_address = regs.depth_htile_data_base.GetAddress();
|
||||
const bool is_clear = regs.depth_render_control.depth_clear_enable ||
|
||||
texture_cache.IsMetaCleared(htile_address);
|
||||
const auto& hint = liverpool->last_db_extent;
|
||||
VideoCore::ImageInfo image_info{regs.depth_buffer, regs.depth_view.NumSlices(),
|
||||
htile_address, hint};
|
||||
VideoCore::ImageViewInfo view_info{regs.depth_buffer, regs.depth_view, regs.depth_control};
|
||||
const auto& image_view = texture_cache.FindDepthTarget(image_info, view_info);
|
||||
const auto& image = texture_cache.GetImage(image_view.image_id);
|
||||
state.width = std::min<u32>(state.width, image.info.size.width);
|
||||
state.height = std::min<u32>(state.height, image.info.size.height);
|
||||
state.depth_image = image.image;
|
||||
state.depth_attachment = {
|
||||
.imageView = *image_view.image_view,
|
||||
.imageLayout = image.last_state.layout,
|
||||
.loadOp = is_clear ? vk::AttachmentLoadOp::eClear : vk::AttachmentLoadOp::eLoad,
|
||||
.storeOp = is_clear ? vk::AttachmentStoreOp::eNone : vk::AttachmentStoreOp::eStore,
|
||||
.clearValue = vk::ClearValue{.depthStencil = {.depth = regs.depth_clear,
|
||||
.stencil = regs.stencil_clear}},
|
||||
};
|
||||
texture_cache.TouchMeta(htile_address, false);
|
||||
state.has_depth =
|
||||
regs.depth_buffer.z_info.format != AmdGpu::Liverpool::DepthBuffer::ZFormat::Invalid;
|
||||
state.has_stencil = regs.depth_buffer.stencil_info.format !=
|
||||
AmdGpu::Liverpool::DepthBuffer::StencilFormat::Invalid;
|
||||
set_writes.clear();
|
||||
buffer_barriers.clear();
|
||||
|
||||
// Bind resource buffers and textures.
|
||||
Shader::PushData push_data{};
|
||||
Shader::Backend::Bindings binding{};
|
||||
|
||||
for (const auto* stage : pipeline->GetStages()) {
|
||||
if (!stage) {
|
||||
continue;
|
||||
}
|
||||
if (stage->uses_step_rates) {
|
||||
push_data.step0 = regs.vgt_instance_step_rate_0;
|
||||
push_data.step1 = regs.vgt_instance_step_rate_1;
|
||||
}
|
||||
stage->PushUd(binding, push_data);
|
||||
|
||||
BindBuffers(*stage, binding, push_data, set_writes, buffer_barriers);
|
||||
BindTextures(*stage, binding, set_writes);
|
||||
}
|
||||
|
||||
pipeline->BindResources(set_writes, buffer_barriers, push_data);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void Rasterizer::BindBuffers(const Shader::Info& stage, Shader::Backend::Bindings& binding,
|
||||
Shader::PushData& push_data, Pipeline::DescriptorWrites& set_writes,
|
||||
Pipeline::BufferBarriers& buffer_barriers) {
|
||||
buffer_bindings.clear();
|
||||
|
||||
for (const auto& desc : stage.buffers) {
|
||||
const auto vsharp = desc.GetSharp(stage);
|
||||
if (!desc.is_gds_buffer && vsharp.base_address != 0 && vsharp.GetSize() > 0) {
|
||||
const auto buffer_id = buffer_cache.FindBuffer(vsharp.base_address, vsharp.GetSize());
|
||||
buffer_bindings.emplace_back(buffer_id, vsharp);
|
||||
} else {
|
||||
buffer_bindings.emplace_back(VideoCore::BufferId{}, vsharp);
|
||||
}
|
||||
}
|
||||
|
||||
texbuffer_bindings.clear();
|
||||
|
||||
for (const auto& desc : stage.texture_buffers) {
|
||||
const auto vsharp = desc.GetSharp(stage);
|
||||
if (vsharp.base_address != 0 && vsharp.GetSize() > 0 &&
|
||||
vsharp.GetDataFmt() != AmdGpu::DataFormat::FormatInvalid) {
|
||||
const auto buffer_id = buffer_cache.FindBuffer(vsharp.base_address, vsharp.GetSize());
|
||||
texbuffer_bindings.emplace_back(buffer_id, vsharp);
|
||||
} else {
|
||||
texbuffer_bindings.emplace_back(VideoCore::BufferId{}, vsharp);
|
||||
}
|
||||
}
|
||||
|
||||
// Bind the flattened user data buffer as a UBO so it's accessible to the shader
|
||||
if (stage.has_readconst) {
|
||||
const auto [vk_buffer, offset] = buffer_cache.ObtainHostUBO(stage.flattened_ud_buf);
|
||||
buffer_infos.emplace_back(vk_buffer->Handle(), offset,
|
||||
stage.flattened_ud_buf.size() * sizeof(u32));
|
||||
set_writes.push_back({
|
||||
.dstSet = VK_NULL_HANDLE,
|
||||
.dstBinding = binding.unified++,
|
||||
.dstArrayElement = 0,
|
||||
.descriptorCount = 1,
|
||||
.descriptorType = vk::DescriptorType::eUniformBuffer,
|
||||
.pBufferInfo = &buffer_infos.back(),
|
||||
});
|
||||
++binding.buffer;
|
||||
}
|
||||
|
||||
// Second pass to re-bind buffers that were updated after binding
|
||||
for (u32 i = 0; i < buffer_bindings.size(); i++) {
|
||||
const auto& [buffer_id, vsharp] = buffer_bindings[i];
|
||||
const auto& desc = stage.buffers[i];
|
||||
const bool is_storage = desc.IsStorage(vsharp);
|
||||
if (!buffer_id) {
|
||||
if (desc.is_gds_buffer) {
|
||||
const auto* gds_buf = buffer_cache.GetGdsBuffer();
|
||||
buffer_infos.emplace_back(gds_buf->Handle(), 0, gds_buf->SizeBytes());
|
||||
} else if (instance.IsNullDescriptorSupported()) {
|
||||
buffer_infos.emplace_back(VK_NULL_HANDLE, 0, VK_WHOLE_SIZE);
|
||||
} else {
|
||||
auto& null_buffer = buffer_cache.GetBuffer(VideoCore::NULL_BUFFER_ID);
|
||||
buffer_infos.emplace_back(null_buffer.Handle(), 0, VK_WHOLE_SIZE);
|
||||
}
|
||||
} else {
|
||||
const auto [vk_buffer, offset] = buffer_cache.ObtainBuffer(
|
||||
vsharp.base_address, vsharp.GetSize(), desc.is_written, false, buffer_id);
|
||||
const u32 alignment =
|
||||
is_storage ? instance.StorageMinAlignment() : instance.UniformMinAlignment();
|
||||
const u32 offset_aligned = Common::AlignDown(offset, alignment);
|
||||
const u32 adjust = offset - offset_aligned;
|
||||
ASSERT(adjust % 4 == 0);
|
||||
push_data.AddOffset(binding.buffer, adjust);
|
||||
buffer_infos.emplace_back(vk_buffer->Handle(), offset_aligned,
|
||||
vsharp.GetSize() + adjust);
|
||||
}
|
||||
|
||||
set_writes.push_back({
|
||||
.dstSet = VK_NULL_HANDLE,
|
||||
.dstBinding = binding.unified++,
|
||||
.dstArrayElement = 0,
|
||||
.descriptorCount = 1,
|
||||
.descriptorType = is_storage ? vk::DescriptorType::eStorageBuffer
|
||||
: vk::DescriptorType::eUniformBuffer,
|
||||
.pBufferInfo = &buffer_infos.back(),
|
||||
});
|
||||
++binding.buffer;
|
||||
}
|
||||
|
||||
const auto null_buffer_view =
|
||||
instance.IsNullDescriptorSupported() ? VK_NULL_HANDLE : buffer_cache.NullBufferView();
|
||||
for (u32 i = 0; i < texbuffer_bindings.size(); i++) {
|
||||
const auto& [buffer_id, vsharp] = texbuffer_bindings[i];
|
||||
const auto& desc = stage.texture_buffers[i];
|
||||
vk::BufferView& buffer_view = buffer_views.emplace_back(null_buffer_view);
|
||||
if (buffer_id) {
|
||||
const u32 alignment = instance.TexelBufferMinAlignment();
|
||||
const auto [vk_buffer, offset] = buffer_cache.ObtainBuffer(
|
||||
vsharp.base_address, vsharp.GetSize(), desc.is_written, true, buffer_id);
|
||||
const u32 fmt_stride = AmdGpu::NumBits(vsharp.GetDataFmt()) >> 3;
|
||||
ASSERT_MSG(fmt_stride == vsharp.GetStride(),
|
||||
"Texel buffer stride must match format stride");
|
||||
const u32 offset_aligned = Common::AlignDown(offset, alignment);
|
||||
const u32 adjust = offset - offset_aligned;
|
||||
ASSERT(adjust % fmt_stride == 0);
|
||||
push_data.AddOffset(binding.buffer, adjust / fmt_stride);
|
||||
buffer_view =
|
||||
vk_buffer->View(offset_aligned, vsharp.GetSize() + adjust, desc.is_written,
|
||||
vsharp.GetDataFmt(), vsharp.GetNumberFmt());
|
||||
if (auto barrier =
|
||||
vk_buffer->GetBarrier(desc.is_written ? vk::AccessFlagBits2::eShaderWrite
|
||||
: vk::AccessFlagBits2::eShaderRead,
|
||||
vk::PipelineStageFlagBits2::eComputeShader)) {
|
||||
buffer_barriers.emplace_back(*barrier);
|
||||
}
|
||||
if (desc.is_written) {
|
||||
texture_cache.InvalidateMemoryFromGPU(vsharp.base_address, vsharp.GetSize());
|
||||
}
|
||||
}
|
||||
|
||||
set_writes.push_back({
|
||||
.dstSet = VK_NULL_HANDLE,
|
||||
.dstBinding = binding.unified++,
|
||||
.dstArrayElement = 0,
|
||||
.descriptorCount = 1,
|
||||
.descriptorType = desc.is_written ? vk::DescriptorType::eStorageTexelBuffer
|
||||
: vk::DescriptorType::eUniformTexelBuffer,
|
||||
.pTexelBufferView = &buffer_view,
|
||||
});
|
||||
++binding.buffer;
|
||||
}
|
||||
}
|
||||
|
||||
void Rasterizer::BindTextures(const Shader::Info& stage, Shader::Backend::Bindings& binding,
|
||||
Pipeline::DescriptorWrites& set_writes) {
|
||||
image_bindings.clear();
|
||||
|
||||
for (const auto& image_desc : stage.images) {
|
||||
const auto tsharp = image_desc.GetSharp(stage);
|
||||
if (texture_cache.IsMeta(tsharp.Address())) {
|
||||
LOG_WARNING(Render_Vulkan, "Unexpected metadata read by a shader (texture)");
|
||||
}
|
||||
|
||||
if (tsharp.GetDataFmt() == AmdGpu::DataFormat::FormatInvalid) {
|
||||
image_bindings.emplace_back(std::piecewise_construct, std::tuple{}, std::tuple{});
|
||||
continue;
|
||||
}
|
||||
|
||||
auto& [image_id, desc] = image_bindings.emplace_back(std::piecewise_construct, std::tuple{},
|
||||
std::tuple{tsharp, image_desc});
|
||||
image_id = texture_cache.FindImage(desc);
|
||||
auto& image = texture_cache.GetImage(image_id);
|
||||
if (image.binding.is_bound) {
|
||||
// The image is already bound. In case if it is about to be used as storage we need
|
||||
// to force general layout on it.
|
||||
image.binding.force_general |= image_desc.is_storage;
|
||||
}
|
||||
if (image.binding.is_target) {
|
||||
// The image is already bound as target. Since we read and output to it need to force
|
||||
// general layout too.
|
||||
image.binding.force_general = 1u;
|
||||
}
|
||||
image.binding.is_bound = 1u;
|
||||
}
|
||||
|
||||
// Second pass to re-bind images that were updated after binding
|
||||
for (auto& [image_id, desc] : image_bindings) {
|
||||
bool is_storage = desc.type == VideoCore::TextureCache::BindingType::Storage;
|
||||
if (!image_id) {
|
||||
if (instance.IsNullDescriptorSupported()) {
|
||||
image_infos.emplace_back(VK_NULL_HANDLE, VK_NULL_HANDLE, vk::ImageLayout::eGeneral);
|
||||
} else {
|
||||
auto& null_image = texture_cache.GetImageView(VideoCore::NULL_IMAGE_VIEW_ID);
|
||||
image_infos.emplace_back(VK_NULL_HANDLE, *null_image.image_view,
|
||||
vk::ImageLayout::eGeneral);
|
||||
}
|
||||
} else {
|
||||
if (auto& old_image = texture_cache.GetImage(image_id);
|
||||
old_image.binding.needs_rebind) {
|
||||
old_image.binding.Reset(); // clean up previous image binding state
|
||||
image_id = texture_cache.FindImage(desc);
|
||||
}
|
||||
|
||||
bound_images.emplace_back(image_id);
|
||||
|
||||
auto& image = texture_cache.GetImage(image_id);
|
||||
auto& image_view = texture_cache.FindTexture(image_id, desc.view_info);
|
||||
|
||||
if (image.binding.force_general || image.binding.is_target) {
|
||||
image.Transit(vk::ImageLayout::eGeneral,
|
||||
vk::AccessFlagBits2::eShaderRead |
|
||||
(image.info.IsDepthStencil()
|
||||
? vk::AccessFlagBits2::eDepthStencilAttachmentWrite
|
||||
: vk::AccessFlagBits2::eColorAttachmentWrite),
|
||||
{});
|
||||
} else {
|
||||
if (is_storage) {
|
||||
image.Transit(vk::ImageLayout::eGeneral,
|
||||
vk::AccessFlagBits2::eShaderRead |
|
||||
vk::AccessFlagBits2::eShaderWrite,
|
||||
desc.view_info.range);
|
||||
} else {
|
||||
const auto new_layout = image.info.IsDepthStencil()
|
||||
? vk::ImageLayout::eDepthStencilReadOnlyOptimal
|
||||
: vk::ImageLayout::eShaderReadOnlyOptimal;
|
||||
image.Transit(new_layout, vk::AccessFlagBits2::eShaderRead,
|
||||
desc.view_info.range);
|
||||
}
|
||||
}
|
||||
image.usage.storage |= is_storage;
|
||||
image.usage.texture |= !is_storage;
|
||||
|
||||
image_infos.emplace_back(VK_NULL_HANDLE, *image_view.image_view,
|
||||
image.last_state.layout);
|
||||
}
|
||||
|
||||
set_writes.push_back({
|
||||
.dstSet = VK_NULL_HANDLE,
|
||||
.dstBinding = binding.unified++,
|
||||
.dstArrayElement = 0,
|
||||
.descriptorCount = 1,
|
||||
.descriptorType =
|
||||
is_storage ? vk::DescriptorType::eStorageImage : vk::DescriptorType::eSampledImage,
|
||||
.pImageInfo = &image_infos.back(),
|
||||
});
|
||||
}
|
||||
|
||||
for (const auto& sampler : stage.samplers) {
|
||||
auto ssharp = sampler.GetSharp(stage);
|
||||
if (sampler.disable_aniso) {
|
||||
const auto& tsharp = stage.images[sampler.associated_image].GetSharp(stage);
|
||||
if (tsharp.base_level == 0 && tsharp.last_level == 0) {
|
||||
ssharp.max_aniso.Assign(AmdGpu::AnisoRatio::One);
|
||||
}
|
||||
}
|
||||
const auto vk_sampler = texture_cache.GetSampler(ssharp);
|
||||
image_infos.emplace_back(vk_sampler, VK_NULL_HANDLE, vk::ImageLayout::eGeneral);
|
||||
set_writes.push_back({
|
||||
.dstSet = VK_NULL_HANDLE,
|
||||
.dstBinding = binding.unified++,
|
||||
.dstArrayElement = 0,
|
||||
.descriptorCount = 1,
|
||||
.descriptorType = vk::DescriptorType::eSampler,
|
||||
.pImageInfo = &image_infos.back(),
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
void Rasterizer::BeginRendering(const GraphicsPipeline& pipeline, RenderState& state) {
|
||||
int cb_index = 0;
|
||||
for (auto& [image_id, desc] : cb_descs) {
|
||||
if (auto& old_img = texture_cache.GetImage(image_id); old_img.binding.needs_rebind) {
|
||||
auto& view = texture_cache.FindRenderTarget(desc);
|
||||
ASSERT(view.image_id != image_id);
|
||||
image_id = bound_images.emplace_back(view.image_id);
|
||||
auto& image = texture_cache.GetImage(view.image_id);
|
||||
state.color_attachments[cb_index].imageView = *view.image_view;
|
||||
state.color_attachments[cb_index].imageLayout = image.last_state.layout;
|
||||
state.color_images[cb_index] = image.image;
|
||||
|
||||
const auto mip = view.info.range.base.level;
|
||||
state.width = std::min<u32>(state.width, std::max(image.info.size.width >> mip, 1u));
|
||||
state.height = std::min<u32>(state.height, std::max(image.info.size.height >> mip, 1u));
|
||||
ASSERT(old_img.info.size.width == state.width);
|
||||
ASSERT(old_img.info.size.height == state.height);
|
||||
}
|
||||
auto& image = texture_cache.GetImage(image_id);
|
||||
if (image.binding.force_general) {
|
||||
image.Transit(
|
||||
vk::ImageLayout::eGeneral,
|
||||
vk::AccessFlagBits2::eColorAttachmentWrite | vk::AccessFlagBits2::eShaderRead, {});
|
||||
|
||||
} else {
|
||||
image.Transit(vk::ImageLayout::eColorAttachmentOptimal,
|
||||
vk::AccessFlagBits2::eColorAttachmentWrite |
|
||||
vk::AccessFlagBits2::eColorAttachmentRead,
|
||||
desc.view_info.range);
|
||||
}
|
||||
image.usage.render_target = 1u;
|
||||
state.color_attachments[cb_index].imageLayout = image.last_state.layout;
|
||||
++cb_index;
|
||||
}
|
||||
|
||||
if (db_desc) {
|
||||
const auto& image_id = std::get<0>(*db_desc);
|
||||
const auto& desc = std::get<1>(*db_desc);
|
||||
auto& image = texture_cache.GetImage(image_id);
|
||||
ASSERT(image.binding.needs_rebind == 0);
|
||||
const bool has_stencil = image.usage.stencil;
|
||||
if (has_stencil) {
|
||||
image.aspect_mask |= vk::ImageAspectFlagBits::eStencil;
|
||||
}
|
||||
if (image.binding.force_general) {
|
||||
image.Transit(vk::ImageLayout::eGeneral,
|
||||
vk::AccessFlagBits2::eDepthStencilAttachmentWrite |
|
||||
vk::AccessFlagBits2::eShaderRead,
|
||||
{});
|
||||
} else {
|
||||
const auto new_layout = desc.view_info.is_storage
|
||||
? has_stencil
|
||||
? vk::ImageLayout::eDepthStencilAttachmentOptimal
|
||||
: vk::ImageLayout::eDepthAttachmentOptimal
|
||||
: has_stencil ? vk::ImageLayout::eDepthStencilReadOnlyOptimal
|
||||
: vk::ImageLayout::eDepthReadOnlyOptimal;
|
||||
image.Transit(new_layout,
|
||||
vk::AccessFlagBits2::eDepthStencilAttachmentWrite |
|
||||
vk::AccessFlagBits2::eDepthStencilAttachmentRead,
|
||||
desc.view_info.range);
|
||||
}
|
||||
state.depth_attachment.imageLayout = image.last_state.layout;
|
||||
image.usage.depth_target = true;
|
||||
image.usage.stencil = has_stencil;
|
||||
}
|
||||
|
||||
scheduler.BeginRendering(state);
|
||||
}
|
||||
|
||||
|
|
@ -328,10 +729,12 @@ void Rasterizer::Resolve() {
|
|||
// Read from MRT0, average all samples, and write to MRT1, which is one-sample
|
||||
const auto& mrt0_hint = liverpool->last_cb_extent[0];
|
||||
const auto& mrt1_hint = liverpool->last_cb_extent[1];
|
||||
VideoCore::ImageInfo mrt0_info{liverpool->regs.color_buffers[0], mrt0_hint};
|
||||
VideoCore::ImageInfo mrt1_info{liverpool->regs.color_buffers[1], mrt1_hint};
|
||||
auto& mrt0_image = texture_cache.GetImage(texture_cache.FindImage(mrt0_info));
|
||||
auto& mrt1_image = texture_cache.GetImage(texture_cache.FindImage(mrt1_info));
|
||||
VideoCore::TextureCache::RenderTargetDesc mrt0_desc{liverpool->regs.color_buffers[0],
|
||||
mrt0_hint};
|
||||
VideoCore::TextureCache::RenderTargetDesc mrt1_desc{liverpool->regs.color_buffers[1],
|
||||
mrt1_hint};
|
||||
auto& mrt0_image = texture_cache.GetImage(texture_cache.FindImage(mrt0_desc));
|
||||
auto& mrt1_image = texture_cache.GetImage(texture_cache.FindImage(mrt1_desc));
|
||||
|
||||
VideoCore::SubresourceRange mrt0_range;
|
||||
mrt0_range.base.layer = liverpool->regs.color_buffers[0].view.slice_start;
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ class MemoryManager;
|
|||
namespace Vulkan {
|
||||
|
||||
class Scheduler;
|
||||
class RenderState;
|
||||
class GraphicsPipeline;
|
||||
|
||||
class Rasterizer {
|
||||
|
|
@ -54,7 +55,8 @@ public:
|
|||
void Finish();
|
||||
|
||||
private:
|
||||
void BeginRendering(const GraphicsPipeline& pipeline);
|
||||
RenderState PrepareRenderState(u32 mrt_mask);
|
||||
void BeginRendering(const GraphicsPipeline& pipeline, RenderState& state);
|
||||
void Resolve();
|
||||
|
||||
void UpdateDynamicState(const GraphicsPipeline& pipeline);
|
||||
|
|
@ -63,6 +65,21 @@ private:
|
|||
|
||||
bool FilterDraw();
|
||||
|
||||
void BindBuffers(const Shader::Info& stage, Shader::Backend::Bindings& binding,
|
||||
Shader::PushData& push_data, Pipeline::DescriptorWrites& set_writes,
|
||||
Pipeline::BufferBarriers& buffer_barriers);
|
||||
|
||||
void BindTextures(const Shader::Info& stage, Shader::Backend::Bindings& binding,
|
||||
Pipeline::DescriptorWrites& set_writes);
|
||||
|
||||
bool BindResources(const Pipeline* pipeline);
|
||||
void ResetBindings() {
|
||||
for (auto& image_id : bound_images) {
|
||||
texture_cache.GetImage(image_id).binding.Reset();
|
||||
}
|
||||
bound_images.clear();
|
||||
}
|
||||
|
||||
private:
|
||||
const Instance& instance;
|
||||
Scheduler& scheduler;
|
||||
|
|
@ -72,6 +89,25 @@ private:
|
|||
AmdGpu::Liverpool* liverpool;
|
||||
Core::MemoryManager* memory;
|
||||
PipelineCache pipeline_cache;
|
||||
|
||||
boost::container::static_vector<
|
||||
std::pair<VideoCore::ImageId, VideoCore::TextureCache::RenderTargetDesc>, 8>
|
||||
cb_descs;
|
||||
std::optional<std::pair<VideoCore::ImageId, VideoCore::TextureCache::DepthTargetDesc>> db_desc;
|
||||
boost::container::static_vector<vk::DescriptorImageInfo, 32> image_infos;
|
||||
boost::container::static_vector<vk::BufferView, 8> buffer_views;
|
||||
boost::container::static_vector<vk::DescriptorBufferInfo, 32> buffer_infos;
|
||||
boost::container::static_vector<VideoCore::ImageId, 64> bound_images;
|
||||
|
||||
Pipeline::DescriptorWrites set_writes;
|
||||
Pipeline::BufferBarriers buffer_barriers;
|
||||
|
||||
using BufferBindingInfo = std::pair<VideoCore::BufferId, AmdGpu::Buffer>;
|
||||
boost::container::static_vector<BufferBindingInfo, 32> buffer_bindings;
|
||||
using TexBufferBindingInfo = std::pair<VideoCore::BufferId, AmdGpu::Buffer>;
|
||||
boost::container::static_vector<TexBufferBindingInfo, 32> texbuffer_bindings;
|
||||
using ImageBindingInfo = std::pair<VideoCore::ImageId, VideoCore::TextureCache::TextureDesc>;
|
||||
boost::container::static_vector<ImageBindingInfo, 32> image_bindings;
|
||||
};
|
||||
|
||||
} // namespace Vulkan
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue