Mirrors/shadPS4
1
0
Fork 0
mirror of https://github.com/shadps4-emu/shadPS4.git synced 2025-05-31 07:43:16 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

Initial support for compiling on ARM64. (#788)

Browse source
This commit is contained in:
squidbus 2024-09-09 03:23:16 -07:00 • committed by GitHub
parent adfb3af95f
commit 411449cd51
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
12 changed files with 166 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

10
src/common/arch.h Normal file
View file

@ -0,0 +1,10 @@
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#pragma once
#if defined(__x86_64__) || defined(_M_X64)
#define ARCH_X86_64 1
#elif defined(__aarch64__) || defined(_M_ARM64)
#define ARCH_ARM64 1
#endif

7
src/common/assert.cpp
View file

@ -1,10 +1,17 @@
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
// SPDX-License-Identifier: GPL-2.0-or-later
#include "common/arch.h"
#include "common/assert.h"
#include "common/logging/backend.h"
#if defined(ARCH_X86_64)
#define Crash() __asm__ __volatile__("int $3")
#elif defined(ARCH_ARM64)
#define Crash() __asm__ __volatile__("brk 0")
#else
#error "Missing Crash() implementation for target CPU architecture."
#endif
void assert_fail_impl() {
Common::Log::Stop();

17
src/common/rdtsc.h
View file

@ -3,6 +3,8 @@
#pragma once
#include "common/arch.h"
#ifdef _MSC_VER
#include <intrin.h>
#endif
@ -13,15 +15,20 @@ namespace Common {
#ifdef _MSC_VER
__forceinline static u64 FencedRDTSC() {
#ifdef ARCH_X86_64
_mm_lfence();
_ReadWriteBarrier();
const u64 result = __rdtsc();
_mm_lfence();
_ReadWriteBarrier();
return result;
#else
#error "Missing FencedRDTSC() implementation for target CPU architecture."
#endif
}
#else
static inline u64 FencedRDTSC() {
#ifdef ARCH_X86_64
u64 eax;
u64 edx;
asm volatile("lfence\n\t"
@ -29,6 +36,16 @@ static inline u64 FencedRDTSC() {
"lfence\n\t"
: "=a"(eax), "=d"(edx));
return (edx << 32) | eax;
#elif defined(ARCH_ARM64)
u64 ret;
asm volatile("isb\n\t"
"mrs %0, cntvct_el0\n\t"
"isb\n\t"
: "=r"(ret)::"memory");
return ret;
#else
#error "Missing FencedRDTSC() implementation for target CPU architecture."
#endif
}
#endif