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https://github.com/shadps4-emu/shadPS4.git
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shader_recompiler: Add swizzle support for unsupported formats. (#1869)
* shader_recompiler: Add swizzle support for unsupported formats. * renderer_vulkan: Rework MRT swizzles and add unsupported format swizzle support. * shader_recompiler: Clean up swizzle handling and handle ImageRead storage swizzle. * shader_recompiler: Fix type errors * liverpool_to_vk: Remove redundant clear color swizzles. * shader_recompiler: Reduce CompositeConstruct to constants where possible. * shader_recompiler: Fix ImageRead/Write and StoreBufferFormatF32 types. * amdgpu: Add a few more unsupported format remaps.
This commit is contained in:
squidbus
GitHub
parent
284f473a52
commit
41d64a200d
22 changed files with 522 additions and 282 deletions
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@ -663,6 +663,86 @@ Value IREmitter::CompositeInsert(const Value& vector, const Value& object, size_
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}
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}
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Value IREmitter::CompositeShuffle(const Value& vector1, const Value& vector2, size_t comp0,
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size_t comp1) {
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if (vector1.Type() != vector2.Type()) {
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UNREACHABLE_MSG("Mismatching types {} and {}", vector1.Type(), vector2.Type());
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}
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if (comp0 >= 4 || comp1 >= 4) {
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UNREACHABLE_MSG("One or more out of bounds elements {}, {}", comp0, comp1);
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}
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const auto shuffle{[&](Opcode opcode) -> Value {
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return Inst(opcode, vector1, vector2, Value{static_cast<u32>(comp0)},
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Value{static_cast<u32>(comp1)});
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}};
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switch (vector1.Type()) {
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case Type::U32x4:
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return shuffle(Opcode::CompositeShuffleU32x2);
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case Type::F16x4:
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return shuffle(Opcode::CompositeShuffleF16x2);
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case Type::F32x4:
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return shuffle(Opcode::CompositeShuffleF32x2);
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case Type::F64x4:
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return shuffle(Opcode::CompositeShuffleF64x2);
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default:
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ThrowInvalidType(vector1.Type());
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}
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}
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Value IREmitter::CompositeShuffle(const Value& vector1, const Value& vector2, size_t comp0,
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size_t comp1, size_t comp2) {
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if (vector1.Type() != vector2.Type()) {
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UNREACHABLE_MSG("Mismatching types {} and {}", vector1.Type(), vector2.Type());
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}
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if (comp0 >= 6 || comp1 >= 6 || comp2 >= 6) {
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UNREACHABLE_MSG("One or more out of bounds elements {}, {}, {}", comp0, comp1, comp2);
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}
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const auto shuffle{[&](Opcode opcode) -> Value {
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return Inst(opcode, vector1, vector2, Value{static_cast<u32>(comp0)},
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Value{static_cast<u32>(comp1)}, Value{static_cast<u32>(comp2)});
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}};
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switch (vector1.Type()) {
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case Type::U32x4:
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return shuffle(Opcode::CompositeShuffleU32x3);
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case Type::F16x4:
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return shuffle(Opcode::CompositeShuffleF16x3);
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case Type::F32x4:
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return shuffle(Opcode::CompositeShuffleF32x3);
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case Type::F64x4:
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return shuffle(Opcode::CompositeShuffleF64x3);
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default:
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ThrowInvalidType(vector1.Type());
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}
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}
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Value IREmitter::CompositeShuffle(const Value& vector1, const Value& vector2, size_t comp0,
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size_t comp1, size_t comp2, size_t comp3) {
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if (vector1.Type() != vector2.Type()) {
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UNREACHABLE_MSG("Mismatching types {} and {}", vector1.Type(), vector2.Type());
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}
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if (comp0 >= 8 || comp1 >= 8 || comp2 >= 8 || comp3 >= 8) {
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UNREACHABLE_MSG("One or more out of bounds elements {}, {}, {}, {}", comp0, comp1, comp2,
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comp3);
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}
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const auto shuffle{[&](Opcode opcode) -> Value {
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return Inst(opcode, vector1, vector2, Value{static_cast<u32>(comp0)},
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Value{static_cast<u32>(comp1)}, Value{static_cast<u32>(comp2)},
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Value{static_cast<u32>(comp3)});
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}};
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switch (vector1.Type()) {
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case Type::U32x4:
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return shuffle(Opcode::CompositeShuffleU32x4);
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case Type::F16x4:
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return shuffle(Opcode::CompositeShuffleF16x4);
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case Type::F32x4:
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return shuffle(Opcode::CompositeShuffleF32x4);
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case Type::F64x4:
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return shuffle(Opcode::CompositeShuffleF64x4);
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default:
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ThrowInvalidType(vector1.Type());
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}
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}
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Value IREmitter::Select(const U1& condition, const Value& true_value, const Value& false_value) {
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if (true_value.Type() != false_value.Type()) {
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UNREACHABLE_MSG("Mismatching types {} and {}", true_value.Type(), false_value.Type());
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@ -155,6 +155,13 @@ public:
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[[nodiscard]] Value CompositeExtract(const Value& vector, size_t element);
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[[nodiscard]] Value CompositeInsert(const Value& vector, const Value& object, size_t element);
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[[nodiscard]] Value CompositeShuffle(const Value& vector1, const Value& vector2, size_t comp0,
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size_t comp1);
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[[nodiscard]] Value CompositeShuffle(const Value& vector1, const Value& vector2, size_t comp0,
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size_t comp1, size_t comp2);
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[[nodiscard]] Value CompositeShuffle(const Value& vector1, const Value& vector2, size_t comp0,
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size_t comp1, size_t comp2, size_t comp3);
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[[nodiscard]] Value Select(const U1& condition, const Value& true_value,
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const Value& false_value);
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@ -99,7 +99,7 @@ OPCODE(StoreBufferU32, Void, Opaq
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OPCODE(StoreBufferU32x2, Void, Opaque, Opaque, U32x2, )
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OPCODE(StoreBufferU32x3, Void, Opaque, Opaque, U32x3, )
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OPCODE(StoreBufferU32x4, Void, Opaque, Opaque, U32x4, )
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OPCODE(StoreBufferFormatF32, Void, Opaque, Opaque, U32x4, )
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OPCODE(StoreBufferFormatF32, Void, Opaque, Opaque, F32x4, )
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// Buffer atomic operations
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OPCODE(BufferAtomicIAdd32, U32, Opaque, Opaque, U32 )
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@ -124,6 +124,9 @@ OPCODE(CompositeExtractU32x4, U32, U32x
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OPCODE(CompositeInsertU32x2, U32x2, U32x2, U32, U32, )
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OPCODE(CompositeInsertU32x3, U32x3, U32x3, U32, U32, )
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OPCODE(CompositeInsertU32x4, U32x4, U32x4, U32, U32, )
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OPCODE(CompositeShuffleU32x2, U32x2, U32x2, U32x2, U32, U32, )
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OPCODE(CompositeShuffleU32x3, U32x3, U32x3, U32x3, U32, U32, U32, )
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OPCODE(CompositeShuffleU32x4, U32x4, U32x4, U32x4, U32, U32, U32, U32, )
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OPCODE(CompositeConstructF16x2, F16x2, F16, F16, )
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OPCODE(CompositeConstructF16x3, F16x3, F16, F16, F16, )
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OPCODE(CompositeConstructF16x4, F16x4, F16, F16, F16, F16, )
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@ -133,6 +136,9 @@ OPCODE(CompositeExtractF16x4, F16, F16x
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OPCODE(CompositeInsertF16x2, F16x2, F16x2, F16, U32, )
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OPCODE(CompositeInsertF16x3, F16x3, F16x3, F16, U32, )
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OPCODE(CompositeInsertF16x4, F16x4, F16x4, F16, U32, )
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OPCODE(CompositeShuffleF16x2, F16x2, F16x2, F16x2, U32, U32, )
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OPCODE(CompositeShuffleF16x3, F16x3, F16x3, F16x3, U32, U32, U32, )
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OPCODE(CompositeShuffleF16x4, F16x4, F16x4, F16x4, U32, U32, U32, U32, )
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OPCODE(CompositeConstructF32x2, F32x2, F32, F32, )
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OPCODE(CompositeConstructF32x3, F32x3, F32, F32, F32, )
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OPCODE(CompositeConstructF32x4, F32x4, F32, F32, F32, F32, )
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@ -142,6 +148,9 @@ OPCODE(CompositeExtractF32x4, F32, F32x
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OPCODE(CompositeInsertF32x2, F32x2, F32x2, F32, U32, )
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OPCODE(CompositeInsertF32x3, F32x3, F32x3, F32, U32, )
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OPCODE(CompositeInsertF32x4, F32x4, F32x4, F32, U32, )
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OPCODE(CompositeShuffleF32x2, F32x2, F32x2, F32x2, U32, U32, )
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OPCODE(CompositeShuffleF32x3, F32x3, F32x3, F32x3, U32, U32, U32, )
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OPCODE(CompositeShuffleF32x4, F32x4, F32x4, F32x4, U32, U32, U32, U32, )
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OPCODE(CompositeConstructF64x2, F64x2, F64, F64, )
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OPCODE(CompositeConstructF64x3, F64x3, F64, F64, F64, )
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OPCODE(CompositeConstructF64x4, F64x4, F64, F64, F64, F64, )
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@ -151,6 +160,9 @@ OPCODE(CompositeExtractF64x4, F64, F64x
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OPCODE(CompositeInsertF64x2, F64x2, F64x2, F64, U32, )
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OPCODE(CompositeInsertF64x3, F64x3, F64x3, F64, U32, )
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OPCODE(CompositeInsertF64x4, F64x4, F64x4, F64, U32, )
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OPCODE(CompositeShuffleF64x2, F64x2, F64x2, F64x2, U32, U32, )
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OPCODE(CompositeShuffleF64x3, F64x3, F64x3, F64x3, U32, U32, U32, )
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OPCODE(CompositeShuffleF64x4, F64x4, F64x4, F64x4, U32, U32, U32, U32, )
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// Select operations
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OPCODE(SelectU1, U1, U1, U1, U1, )
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@ -346,8 +358,8 @@ OPCODE(ImageGatherDref, F32x4, Opaq
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OPCODE(ImageQueryDimensions, U32x4, Opaque, U32, U1, )
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OPCODE(ImageQueryLod, F32x4, Opaque, Opaque, )
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OPCODE(ImageGradient, F32x4, Opaque, Opaque, Opaque, Opaque, Opaque, F32, )
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OPCODE(ImageRead, U32x4, Opaque, Opaque, U32, U32, )
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OPCODE(ImageWrite, Void, Opaque, Opaque, U32, U32, U32x4, )
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OPCODE(ImageRead, F32x4, Opaque, Opaque, U32, U32, )
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OPCODE(ImageWrite, Void, Opaque, Opaque, U32, U32, F32x4, )
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// Image atomic operations
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OPCODE(ImageAtomicIAdd32, U32, Opaque, Opaque, U32, )
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@ -8,6 +8,7 @@
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#include "shader_recompiler/ir/breadth_first_search.h"
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#include "shader_recompiler/ir/ir_emitter.h"
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#include "shader_recompiler/ir/program.h"
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#include "shader_recompiler/ir/reinterpret.h"
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#include "video_core/amdgpu/resource.h"
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namespace Shader::Optimization {
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@ -128,35 +129,6 @@ bool IsImageInstruction(const IR::Inst& inst) {
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}
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}
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IR::Value SwizzleVector(IR::IREmitter& ir, auto sharp, IR::Value texel) {
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boost::container::static_vector<IR::Value, 4> comps;
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for (u32 i = 0; i < 4; i++) {
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switch (sharp.GetSwizzle(i)) {
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case AmdGpu::CompSwizzle::Zero:
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comps.emplace_back(ir.Imm32(0.f));
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break;
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case AmdGpu::CompSwizzle::One:
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comps.emplace_back(ir.Imm32(1.f));
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break;
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case AmdGpu::CompSwizzle::Red:
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comps.emplace_back(ir.CompositeExtract(texel, 0));
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break;
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case AmdGpu::CompSwizzle::Green:
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comps.emplace_back(ir.CompositeExtract(texel, 1));
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break;
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case AmdGpu::CompSwizzle::Blue:
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comps.emplace_back(ir.CompositeExtract(texel, 2));
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break;
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case AmdGpu::CompSwizzle::Alpha:
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comps.emplace_back(ir.CompositeExtract(texel, 3));
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break;
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default:
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UNREACHABLE();
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}
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}
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return ir.CompositeConstruct(comps[0], comps[1], comps[2], comps[3]);
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};
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class Descriptors {
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public:
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explicit Descriptors(Info& info_)
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@ -409,15 +381,6 @@ void PatchTextureBufferInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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inst.SetArg(0, ir.Imm32(binding));
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ASSERT(!buffer.swizzle_enable && !buffer.add_tid_enable);
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// Apply dst_sel swizzle on formatted buffer instructions
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if (inst.GetOpcode() == IR::Opcode::StoreBufferFormatF32) {
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inst.SetArg(2, SwizzleVector(ir, buffer, inst.Arg(2)));
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} else {
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const auto inst_info = inst.Flags<IR::BufferInstInfo>();
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const auto texel = ir.LoadBufferFormat(inst.Arg(0), inst.Arg(1), inst_info);
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inst.ReplaceUsesWith(SwizzleVector(ir, buffer, texel));
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}
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}
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IR::Value PatchCubeCoord(IR::IREmitter& ir, const IR::Value& s, const IR::Value& t,
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@ -765,10 +728,6 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
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}();
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inst.SetArg(1, coords);
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if (inst.GetOpcode() == IR::Opcode::ImageWrite) {
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inst.SetArg(4, SwizzleVector(ir, image, inst.Arg(4)));
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}
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if (inst_info.has_lod) {
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ASSERT(inst.GetOpcode() == IR::Opcode::ImageRead ||
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inst.GetOpcode() == IR::Opcode::ImageWrite);
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@ -783,6 +742,50 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
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}
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}
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void PatchTextureBufferInterpretation(IR::Block& block, IR::Inst& inst, Info& info) {
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const auto binding = inst.Arg(0).U32();
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const auto buffer_res = info.texture_buffers[binding];
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const auto buffer = buffer_res.GetSharp(info);
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if (!buffer.Valid()) {
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// Don't need to swizzle invalid buffer.
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return;
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}
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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if (inst.GetOpcode() == IR::Opcode::StoreBufferFormatF32) {
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inst.SetArg(2, ApplySwizzle(ir, inst.Arg(2), buffer.DstSelect()));
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} else if (inst.GetOpcode() == IR::Opcode::LoadBufferFormatF32) {
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const auto inst_info = inst.Flags<IR::BufferInstInfo>();
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const auto texel = ir.LoadBufferFormat(inst.Arg(0), inst.Arg(1), inst_info);
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const auto swizzled = ApplySwizzle(ir, texel, buffer.DstSelect());
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inst.ReplaceUsesWith(swizzled);
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}
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}
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void PatchImageInterpretation(IR::Block& block, IR::Inst& inst, Info& info) {
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const auto binding = inst.Arg(0).U32();
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const auto image_res = info.images[binding & 0xFFFF];
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const auto image = image_res.GetSharp(info);
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if (!image.Valid() || !image_res.IsStorage(image)) {
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// Don't need to swizzle invalid or non-storage image.
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return;
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}
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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if (inst.GetOpcode() == IR::Opcode::ImageWrite) {
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inst.SetArg(4, ApplySwizzle(ir, inst.Arg(4), image.DstSelect()));
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} else if (inst.GetOpcode() == IR::Opcode::ImageRead) {
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const auto inst_info = inst.Flags<IR::TextureInstInfo>();
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const auto lod = inst.Arg(2);
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const auto ms = inst.Arg(3);
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const auto texel =
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ir.ImageRead(inst.Arg(0), inst.Arg(1), lod.IsEmpty() ? IR::U32{} : IR::U32{lod},
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ms.IsEmpty() ? IR::U32{} : IR::U32{ms}, inst_info);
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const auto swizzled = ApplySwizzle(ir, texel, image.DstSelect());
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inst.ReplaceUsesWith(swizzled);
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}
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}
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void PatchDataRingInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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Descriptors& descriptors) {
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// Insert gds binding in the shader if it doesn't exist already.
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@ -852,6 +855,19 @@ void ResourceTrackingPass(IR::Program& program) {
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}
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}
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}
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// Second pass to reinterpret format read/write where needed, since we now know
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// the bindings and their properties.
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for (IR::Block* const block : program.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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if (IsTextureBufferInstruction(inst)) {
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PatchTextureBufferInterpretation(*block, inst, info);
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continue;
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}
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if (IsImageInstruction(inst)) {
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PatchImageInterpretation(*block, inst, info);
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}
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}
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}
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}
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} // namespace Shader::Optimization
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24
src/shader_recompiler/ir/reinterpret.h
Normal file
24
src/shader_recompiler/ir/reinterpret.h
Normal file
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@ -0,0 +1,24 @@
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include "shader_recompiler/ir/ir_emitter.h"
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#include "video_core/amdgpu/resource.h"
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namespace Shader::IR {
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/// Applies a component swizzle to a vec4.
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inline Value ApplySwizzle(IREmitter& ir, const Value& vector, const AmdGpu::CompMapping& swizzle) {
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// Constants are indexed as 0 and 1, and components are 4-7. Thus we can apply a swizzle
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// using two vectors and a shuffle, using one vector of constants and one of the components.
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const auto zero = ir.Imm32(0.f);
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const auto one = ir.Imm32(1.f);
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const auto constants_vec = ir.CompositeConstruct(zero, one, zero, zero);
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const auto swizzled =
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ir.CompositeShuffle(constants_vec, vector, size_t(swizzle.r), size_t(swizzle.g),
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size_t(swizzle.b), size_t(swizzle.a));
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return swizzled;
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}
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} // namespace Shader::IR
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