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hotfix: 64-bit shift fixups

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squidbus 2025-01-24 03:11:13 -08:00
parent 9dcf40e261
commit 4d12de8149
7 changed files with 27 additions and 29 deletions
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23
src/shader_recompiler/frontend/translate/vector_alu.cpp
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@ -1257,28 +1257,7 @@ void Translator::V_CVT_PK_U8_F32(const GcnInst& inst) {
void Translator::V_LSHL_B64(const GcnInst& inst) {
const IR::U64 src0{GetSrc64(inst.src[0])};
const IR::U64 src1{GetSrc64(inst.src[1])};
const IR::VectorReg dst_reg{inst.dst[0].code};
if (src0.IsImmediate()) {
if (src0.U64() == -1) {
// If src0 is a fixed -1, the result will always be -1.
ir.SetVectorReg(dst_reg, ir.Imm32(0xFFFFFFFF));
ir.SetVectorReg(dst_reg + 1, ir.Imm32(0xFFFFFFFF));
return;
}
if (src1.IsImmediate()) {
// If both src0 and src1 are immediates, we can calculate the result now.
// Note that according to the manual, only bits 4:0 are used from src1.
const u64 result = src0.U64() << (src1.U64() & 0x1F);
ir.SetVectorReg(dst_reg, ir.Imm32(static_cast<u32>(result)));
ir.SetVectorReg(dst_reg + 1, ir.Imm32(static_cast<u32>(result >> 32)));
return;
}
const IR::U64 result = ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm64(u64(0x3F))));
SetDst64(inst.dst[0], result);
return;
}
UNREACHABLE_MSG("Unimplemented V_LSHL_B64 arguments");
SetDst64(inst.dst[0], ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm64(u64(0x3F)))));
}
void Translator::V_MUL_F64(const GcnInst& inst) {