mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-18 17:34:52 +00:00
video_core: Implement basic compute shaders and more instructions
This commit is contained in:
raphaelthegreat
parent
10bceb1643
commit
58de7ff55a
58 changed files with 1234 additions and 293 deletions
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@ -9,7 +9,18 @@
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namespace Shader::Gcn {
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Translator::Translator(IR::Block* block_, Info& info_) : block{block_}, ir{*block}, info{info_} {
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Translator::Translator(IR::Block* block_, Info& info_)
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: ir{*block_, block_->begin()}, info{info_} {}
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void Translator::EmitPrologue() {
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ir.Prologue();
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// Initialize user data.
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IR::ScalarReg dst_sreg = IR::ScalarReg::S0;
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for (u32 i = 0; i < info.num_user_data; i++) {
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ir.SetScalarReg(dst_sreg++, ir.GetUserData(dst_sreg));
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}
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IR::VectorReg dst_vreg = IR::VectorReg::V0;
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switch (info.stage) {
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case Stage::Vertex:
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@ -29,69 +40,108 @@ Translator::Translator(IR::Block* block_, Info& info_) : block{block_}, ir{*bloc
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}
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::IsFrontFace));
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break;
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case Stage::Compute:
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 0));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 1));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 2));
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 0));
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 1));
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 2));
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break;
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default:
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throw NotImplementedException("Unknown shader stage");
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}
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// Initialize user data.
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IR::ScalarReg dst_sreg = IR::ScalarReg::S0;
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for (u32 i = 0; i < 16; i++) {
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ir.SetScalarReg(dst_sreg++, ir.GetUserData(dst_sreg));
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}
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}
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IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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IR::U32F32 value{};
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (operand.type == ScalarType::Float32 || force_flt) {
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return ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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value = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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} else {
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return ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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value = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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}
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break;
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case OperandField::VectorGPR:
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if (operand.type == ScalarType::Float32 || force_flt) {
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return ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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value = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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} else {
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return ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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value = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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}
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break;
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case OperandField::ConstZero:
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if (force_flt) {
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return ir.Imm32(0.f);
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value = ir.Imm32(0.f);
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} else {
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return ir.Imm32(0U);
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value = ir.Imm32(0U);
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}
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break;
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case OperandField::SignedConstIntPos:
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ASSERT(!force_flt);
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return ir.Imm32(operand.code - SignedConstIntPosMin + 1);
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value = ir.Imm32(operand.code - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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ASSERT(!force_flt);
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return ir.Imm32(-s32(operand.code) + SignedConstIntNegMin - 1);
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value = ir.Imm32(-s32(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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ASSERT(!force_flt);
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return ir.Imm32(operand.code);
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if (force_flt) {
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value = ir.Imm32(std::bit_cast<float>(operand.code));
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} else {
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value = ir.Imm32(operand.code);
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}
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break;
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case OperandField::ConstFloatPos_1_0:
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return ir.Imm32(1.f);
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value = ir.Imm32(1.f);
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break;
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case OperandField::ConstFloatPos_0_5:
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return ir.Imm32(0.5f);
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value = ir.Imm32(0.5f);
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break;
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case OperandField::ConstFloatPos_2_0:
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return ir.Imm32(2.0f);
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value = ir.Imm32(2.0f);
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break;
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case OperandField::ConstFloatPos_4_0:
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return ir.Imm32(4.0f);
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value = ir.Imm32(4.0f);
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break;
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case OperandField::ConstFloatNeg_0_5:
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return ir.Imm32(-0.5f);
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value = ir.Imm32(-0.5f);
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break;
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case OperandField::ConstFloatNeg_1_0:
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return ir.Imm32(-1.0f);
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value = ir.Imm32(-1.0f);
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break;
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case OperandField::VccLo:
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value = ir.GetVccLo();
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break;
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default:
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UNREACHABLE();
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}
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(value);
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}
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return value;
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}
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void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
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IR::U32F32 result = value;
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if (operand.output_modifier.multiplier != 0.f) {
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result = ir.FPMul(result, ir.Imm32(operand.output_modifier.multiplier));
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}
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if (operand.output_modifier.clamp) {
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result = ir.FPSaturate(value);
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}
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switch (operand.field) {
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case OperandField::ScalarGPR:
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return ir.SetScalarReg(IR::ScalarReg(operand.code), value);
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return ir.SetScalarReg(IR::ScalarReg(operand.code), result);
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case OperandField::VectorGPR:
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return ir.SetVectorReg(IR::VectorReg(operand.code), value);
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return ir.SetVectorReg(IR::VectorReg(operand.code), result);
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case OperandField::VccLo:
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return ir.SetVccLo(result);
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case OperandField::VccHi:
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case OperandField::M0:
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break; // Ignore for now
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@ -168,6 +218,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_CVT_F32_U32:
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translator.V_CVT_F32_U32(inst);
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break;
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case Opcode::V_RCP_F32:
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translator.V_RCP_F32(inst);
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break;
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case Opcode::S_SWAPPC_B64:
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ASSERT(info.stage == Stage::Vertex);
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translator.EmitFetch(inst);
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@ -198,18 +251,81 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_CVT_PKRTZ_F16_F32:
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translator.V_CVT_PKRTZ_F16_F32(inst);
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break;
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case Opcode::V_FRACT_F32:
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translator.V_FRACT_F32(inst);
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break;
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case Opcode::V_ADD_F32:
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translator.V_ADD_F32(inst);
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break;
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case Opcode::V_CVT_OFF_F32_I4:
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translator.V_CVT_OFF_F32_I4(inst);
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break;
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case Opcode::V_MED3_F32:
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translator.V_MED3_F32(inst);
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break;
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case Opcode::V_FLOOR_F32:
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translator.V_FLOOR_F32(inst);
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break;
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case Opcode::V_SUB_F32:
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translator.V_SUB_F32(inst);
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break;
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case Opcode::V_FMA_F32:
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case Opcode::V_MADAK_F32: // Yes these can share the opcode
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translator.V_FMA_F32(inst);
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break;
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case Opcode::IMAGE_SAMPLE:
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translator.IMAGE_SAMPLE(inst);
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break;
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case Opcode::V_CMP_EQ_U32:
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translator.V_CMP_EQ_U32(inst);
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break;
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case Opcode::V_CMPX_GT_U32:
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translator.V_CMPX_GT_U32(inst);
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break;
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case Opcode::V_CMP_F_F32:
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translator.V_CMP_F32(ConditionOp::F, inst);
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break;
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case Opcode::V_CMP_LT_F32:
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translator.V_CMP_F32(ConditionOp::LT, inst);
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break;
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case Opcode::V_CMP_EQ_F32:
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translator.V_CMP_F32(ConditionOp::EQ, inst);
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break;
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case Opcode::V_CMP_LE_F32:
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translator.V_CMP_F32(ConditionOp::LE, inst);
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break;
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case Opcode::V_CMP_GT_F32:
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translator.V_CMP_F32(ConditionOp::GT, inst);
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break;
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case Opcode::V_CMP_LG_F32:
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translator.V_CMP_F32(ConditionOp::LG, inst);
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break;
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case Opcode::V_CMP_GE_F32:
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translator.V_CMP_F32(ConditionOp::GE, inst);
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break;
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case Opcode::S_CMP_LG_U32:
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translator.S_CMP(ConditionOp::LG, false, inst);
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break;
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case Opcode::V_CNDMASK_B32:
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translator.V_CNDMASK_B32(inst);
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break;
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case Opcode::TBUFFER_LOAD_FORMAT_XYZW:
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translator.TBUFFER_LOAD_FORMAT_XYZW(inst);
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translator.BUFFER_LOAD_FORMAT(4, true, inst);
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break;
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case Opcode::BUFFER_LOAD_FORMAT_X:
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translator.BUFFER_LOAD_FORMAT(1, false, inst);
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break;
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case Opcode::BUFFER_STORE_FORMAT_X:
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translator.BUFFER_STORE_FORMAT(1, false, inst);
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break;
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case Opcode::V_MAX_F32:
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translator.V_MAX_F32(inst);
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break;
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case Opcode::S_ANDN2_B64:
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translator.S_ANDN2_B64(inst);
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break;
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case Opcode::S_CBRANCH_EXECZ:
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case Opcode::S_CBRANCH_SCC0:
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case Opcode::S_MOV_B64:
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case Opcode::S_WQM_B64:
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case Opcode::V_INTERP_P1_F32:
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