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shader: Fix block processing order in dead code elimination pass

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This commit is contained in:
raphaelthegreat 2024-06-06 02:24:30 +03:00
parent 705d326a6d
commit 5aa3a4d4a0
10 changed files with 60 additions and 75 deletions
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1
src/shader_recompiler/frontend/control_flow_graph.h
View file

@ -41,6 +41,7 @@ struct Block : Hook {
EndClass end_class{};
Block* branch_true{};
Block* branch_false{};
bool is_dummy{};
};
class CFG {

10
src/shader_recompiler/frontend/structured_control_flow.cpp
View file

@ -630,9 +630,11 @@ private:
break;
case StatementType::Code: {
ensure_block();
const u32 start = stmt.block->begin_index;
const u32 size = stmt.block->end_index - start + 1;
Translate(current_block, inst_list.subspan(start, size), info);
if (!stmt.block->is_dummy) {
const u32 start = stmt.block->begin_index;
const u32 size = stmt.block->end_index - start + 1;
Translate(current_block, inst_list.subspan(start, size), info);
}
break;
}
case StatementType::SetVariable: {
@ -808,7 +810,7 @@ private:
ObjectPool<IR::Inst>& inst_pool;
ObjectPool<IR::Block>& block_pool;
IR::AbstractSyntaxList& syntax_list;
const Block dummy_flow_block{};
const Block dummy_flow_block{.is_dummy = true};
std::span<const GcnInst> inst_list;
Info& info;
};

9
src/shader_recompiler/frontend/translate/scalar_alu.cpp
View file

@ -104,18 +104,21 @@ void Translator::S_MOV_B64(const GcnInst& inst) {
if (inst.src[0].field == OperandField::VccLo || inst.dst[0].field == OperandField::VccLo) {
return;
}
const IR::U1 src0{GetSrc(inst.src[0])};
if (inst.dst[0].field == OperandField::ScalarGPR && inst.src[0].field == OperandField::ExecLo) {
// Exec context push
exec_contexts[inst.dst[0].code] = true;
ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[0].code), ir.GetExec());
} else if (inst.dst[0].field == OperandField::ExecLo &&
inst.src[0].field == OperandField::ScalarGPR) {
// Exec context pop
exec_contexts[inst.src[0].code] = false;
} else if (inst.src[0].field != OperandField::ConstZero) {
ir.SetExec(ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code)));
} else if (inst.dst[0].field == OperandField::ExecLo &&
inst.src[0].field == OperandField::ConstZero) {
ir.SetExec(ir.Imm1(false));
} else {
UNREACHABLE();
}
SetDst(inst.dst[0], src0);
}
void Translator::S_OR_B64(bool negate, const GcnInst& inst) {

19
src/shader_recompiler/frontend/translate/translate.cpp
View file

@ -58,16 +58,13 @@ void Translator::EmitPrologue() {
}
}
IR::U1U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
// Input modifiers work on float values.
force_flt |= operand.input_modifier.abs | operand.input_modifier.neg;
IR::U1U32F32 value{};
IR::U32F32 value{};
switch (operand.field) {
case OperandField::ScalarGPR:
if (exec_contexts[operand.code]) {
value = ir.GetThreadBitScalarReg(IR::ScalarReg(operand.code));
}
if (operand.type == ScalarType::Float32 || force_flt) {
value = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
} else {
@ -124,9 +121,6 @@ IR::U1U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
case OperandField::ConstFloatNeg_2_0:
value = ir.Imm32(-2.0f);
break;
case OperandField::ExecLo:
value = ir.GetExec();
break;
case OperandField::VccLo:
if (force_flt) {
value = ir.BitCast<IR::F32>(ir.GetVccLo());
@ -150,8 +144,8 @@ IR::U1U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
return value;
}
void Translator::SetDst(const InstOperand& operand, const IR::U1U32F32& value) {
IR::U1U32F32 result = value;
void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
IR::U32F32 result = value;
if (operand.output_modifier.multiplier != 0.f) {
result = ir.FPMul(result, ir.Imm32(operand.output_modifier.multiplier));
}
@ -160,14 +154,9 @@ void Translator::SetDst(const InstOperand& operand, const IR::U1U32F32& value) {
}
switch (operand.field) {
case OperandField::ScalarGPR:
if (value.Type() == IR::Type::U1) {
return ir.SetThreadBitScalarReg(IR::ScalarReg(operand.code), result);
}
return ir.SetScalarReg(IR::ScalarReg(operand.code), result);
case OperandField::VectorGPR:
return ir.SetVectorReg(IR::VectorReg(operand.code), result);
case OperandField::ExecLo:
return ir.SetExec(result);
case OperandField::VccLo:
return ir.SetVccLo(result);
case OperandField::VccHi:

4
src/shader_recompiler/frontend/translate/translate.h
View file

@ -124,8 +124,8 @@ public:
void EXP(const GcnInst& inst);
private:
IR::U1U32F32 GetSrc(const InstOperand& operand, bool flt_zero = false);
void SetDst(const InstOperand& operand, const IR::U1U32F32& value);
IR::U32F32 GetSrc(const InstOperand& operand, bool flt_zero = false);
void SetDst(const InstOperand& operand, const IR::U32F32& value);
private:
IR::IREmitter ir;