From 5c5c02cb040895bcab7abb7932efe12b240a04e0 Mon Sep 17 00:00:00 2001 From: Raven Date: Sat, 14 Sep 2024 23:52:30 +0800 Subject: [PATCH] Add S_XOR_B32 opcode (#911) * Add S_XOR_B32 * Stub S_OR_B32 --- .../frontend/translate/scalar_alu.cpp | 10 ++++++++++ src/shader_recompiler/frontend/translate/translate.h | 1 + 2 files changed, 11 insertions(+) diff --git a/src/shader_recompiler/frontend/translate/scalar_alu.cpp b/src/shader_recompiler/frontend/translate/scalar_alu.cpp index 4feec2c12..e246b5c51 100644 --- a/src/shader_recompiler/frontend/translate/scalar_alu.cpp +++ b/src/shader_recompiler/frontend/translate/scalar_alu.cpp @@ -55,6 +55,8 @@ void Translator::EmitScalarAlu(const GcnInst& inst) { return S_ASHR_I32(inst); case Opcode::S_OR_B32: return S_OR_B32(inst); + case Opcode::S_XOR_B32: + return S_XOR_B32(inst); case Opcode::S_LSHL_B32: return S_LSHL_B32(inst); case Opcode::S_LSHR_B32: @@ -417,6 +419,14 @@ void Translator::S_OR_B32(const GcnInst& inst) { ir.SetScc(ir.INotEqual(result, ir.Imm32(0))); } +void Translator::S_XOR_B32(const GcnInst& inst) { + const IR::U32 src0{GetSrc(inst.src[0])}; + const IR::U32 src1{GetSrc(inst.src[1])}; + const IR::U32 result{ir.BitwiseXor(src0, src1)}; + SetDst(inst.dst[0], result); + ir.SetScc(ir.INotEqual(result, ir.Imm32(0))); +} + void Translator::S_LSHR_B32(const GcnInst& inst) { const IR::U32 src0{GetSrc(inst.src[0])}; const IR::U32 src1{GetSrc(inst.src[1])}; diff --git a/src/shader_recompiler/frontend/translate/translate.h b/src/shader_recompiler/frontend/translate/translate.h index bd197628d..cdbc93306 100644 --- a/src/shader_recompiler/frontend/translate/translate.h +++ b/src/shader_recompiler/frontend/translate/translate.h @@ -87,6 +87,7 @@ public: void S_AND_B32(NegateMode negate, const GcnInst& inst); void S_ASHR_I32(const GcnInst& inst); void S_OR_B32(const GcnInst& inst); + void S_XOR_B32(const GcnInst& inst); void S_LSHR_B32(const GcnInst& inst); void S_CSELECT_B32(const GcnInst& inst); void S_CSELECT_B64(const GcnInst& inst);