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https://github.com/shadps4-emu/shadPS4.git
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spirv: Add fragdepth and implement image query
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parent
1f83824a8a
commit
5da79d4798
10 changed files with 51 additions and 17 deletions
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@ -104,7 +104,7 @@ void Translator::S_MOV_B64(const GcnInst& inst) {
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}
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}
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void Translator::S_OR_B64(NegateMode negate, const GcnInst& inst) {
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void Translator::S_OR_B64(NegateMode negate, bool is_xor, const GcnInst& inst) {
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const auto get_src = [&](const InstOperand& operand) {
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switch (operand.field) {
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case OperandField::ExecLo:
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@ -123,7 +123,7 @@ void Translator::S_OR_B64(NegateMode negate, const GcnInst& inst) {
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if (negate == NegateMode::Src1) {
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src1 = ir.LogicalNot(src1);
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}
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IR::U1 result = ir.LogicalOr(src0, src1);
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IR::U1 result = is_xor ? ir.LogicalXor(src0, src1) : ir.LogicalOr(src0, src1);
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if (negate == NegateMode::Result) {
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result = ir.LogicalNot(result);
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}
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@ -406,6 +406,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_CMP_NLT_F32:
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translator.V_CMP_F32(ConditionOp::GE, false, inst);
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break;
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case Opcode::V_CMP_NGT_F32:
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translator.V_CMP_F32(ConditionOp::LE, false, inst);
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break;
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case Opcode::S_CMP_LT_U32:
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translator.S_CMP(ConditionOp::LT, false, inst);
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break;
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@ -473,7 +476,7 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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translator.S_AND_B64(NegateMode::Src1, inst);
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break;
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case Opcode::S_ORN2_B64:
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translator.S_OR_B64(NegateMode::Src1, inst);
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translator.S_OR_B64(NegateMode::Src1, false, inst);
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break;
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case Opcode::V_SIN_F32:
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translator.V_SIN_F32(inst);
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@ -612,10 +615,13 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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translator.V_CMP_U32(ConditionOp::TRU, false, true, inst);
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break;
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case Opcode::S_OR_B64:
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translator.S_OR_B64(NegateMode::None, inst);
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translator.S_OR_B64(NegateMode::None, false, inst);
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break;
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case Opcode::S_NOR_B64:
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translator.S_OR_B64(NegateMode::Result, inst);
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translator.S_OR_B64(NegateMode::Result, false, inst);
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break;
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case Opcode::S_XOR_B64:
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translator.S_OR_B64(NegateMode::None, true, inst);
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break;
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case Opcode::S_AND_B64:
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translator.S_AND_B64(NegateMode::None, inst);
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@ -739,6 +745,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_RCP_IFLAG_F32:
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translator.V_RCP_F32(inst);
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break;
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case Opcode::IMAGE_GET_RESINFO:
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translator.IMAGE_GET_RESINFO(inst);
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break;
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case Opcode::S_TTRACEDATA:
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LOG_WARNING(Render_Vulkan, "S_TTRACEDATA instruction!");
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break;
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@ -46,7 +46,7 @@ public:
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void S_CMP(ConditionOp cond, bool is_signed, const GcnInst& inst);
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void S_AND_SAVEEXEC_B64(const GcnInst& inst);
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void S_MOV_B64(const GcnInst& inst);
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void S_OR_B64(NegateMode negate, const GcnInst& inst);
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void S_OR_B64(NegateMode negate, bool is_xor, const GcnInst& inst);
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void S_AND_B64(NegateMode negate, const GcnInst& inst);
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void S_ADD_I32(const GcnInst& inst);
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void S_AND_B32(const GcnInst& inst);
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@ -6,14 +6,13 @@
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namespace Shader::Gcn {
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void Translator::IMAGE_GET_RESINFO(const GcnInst& inst) {
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IR::VectorReg dst_reg{inst.src[1].code};
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IR::VectorReg dst_reg{inst.dst[0].code};
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const IR::ScalarReg tsharp_reg{inst.src[2].code};
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const auto flags = ImageResFlags(inst.control.mimg.dmask);
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const bool has_mips = flags.test(ImageResComponent::MipCount);
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const IR::U32 lod = ir.GetVectorReg(IR::VectorReg(inst.src[0].code));
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const IR::Value tsharp =
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ir.CompositeConstruct(ir.GetScalarReg(tsharp_reg), ir.GetScalarReg(tsharp_reg + 1),
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ir.GetScalarReg(tsharp_reg + 2), ir.GetScalarReg(tsharp_reg + 3));
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const IR::Value size = ir.ImageQueryDimension(tsharp, lod, ir.Imm1(false));
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const IR::Value tsharp = ir.GetScalarReg(tsharp_reg);
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const IR::Value size = ir.ImageQueryDimension(tsharp, lod, ir.Imm1(has_mips));
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if (flags.test(ImageResComponent::Width)) {
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 0)});
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@ -24,7 +23,7 @@ void Translator::IMAGE_GET_RESINFO(const GcnInst& inst) {
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if (flags.test(ImageResComponent::Depth)) {
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 2)});
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}
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if (flags.test(ImageResComponent::MipCount)) {
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if (has_mips) {
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 3)});
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}
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}
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