Surface management rework (1/3) (#307)

* amdgpu: proper CB and DB sizes calculation; minor refactoring

* texture_cache: separate file for image_info

* texture_cache: image guest address moved into image info

* texture_cache: surface size calculation

* shader_recompiler: fixed sin/cos

Thanks to red_pring and gandalfthewhite0173

* initial preparations for subresources upload

* review comments

src/video_core/amdgpu/liverpool.h

@@ -321,7 +321,7 @@ struct Liverpool {
 
     struct DepthBuffer {
         enum class ZFormat : u32 {
-            Invald = 0,
+            Invalid = 0,
             Z16 = 1,
             Z32Float = 3,
         };
@@ -367,8 +367,14 @@ struct Liverpool {
             return u64(z_read_base) << 8;
         }
 
-        size_t GetSizeAligned() const {
-            return depth_slice.tile_max * 8;
+        u32 NumSamples() const {
+            return 1u << z_info.num_samples; // spec doesn't say it is a log2
+        }
+
+        size_t GetDepthSliceSize() const {
+            ASSERT(z_info.format != ZFormat::Invalid);
+            const auto bpe = z_info.format == ZFormat::Z32Float ? 4 : 2;
+            return (depth_slice.tile_max + 1) * 64 * bpe * NumSamples();
         }
     };
 
@@ -733,12 +739,19 @@ struct Liverpool {
             return VAddr(fmask_base_address) << 8;
         }
 
-        size_t GetSizeAligned() const {
+        u32 NumSamples() const {
+            return 1 << attrib.num_fragments_log2;
+        }
+
+        u32 NumSlices() const {
+            return view.slice_max + 1;
+        }
+
+        size_t GetColorSliceSize() const {
             const auto num_bytes_per_element = NumBits(info.format) / 8u;
-            const auto slice_size = (slice.tile_max + 1) * 64u;
-            const auto total_size = slice_size * (view.slice_max + 1) * num_bytes_per_element;
-            ASSERT(total_size > 0);
-            return total_size;
+            const auto slice_size =
+                num_bytes_per_element * (slice.tile_max + 1) * 64u * NumSamples();
+            return slice_size;
         }
 
         TilingMode GetTilingMode() const {
@@ -819,6 +832,17 @@ struct Liverpool {
         BitField<6, 1, u32> depth_compress_disable;
     };
 
+    union DepthView {
+        BitField<0, 11, u32> slice_start;
+        BitField<13, 11, u32> slice_max;
+        BitField<24, 1, u32> z_read_only;
+        BitField<25, 1, u32> stencil_read_only;
+
+        u32 NumSlices() const {
+            return slice_max + 1u;
+        }
+    };
+
     union AaConfig {
         BitField<0, 3, u32> msaa_num_samples;
         BitField<4, 1, u32> aa_mask_centroid_dtmn;
@@ -849,7 +873,9 @@ struct Liverpool {
             ComputeProgram cs_program;
             INSERT_PADDING_WORDS(0xA008 - 0x2E00 - 80 - 3 - 5);
             DepthRenderControl depth_render_control;
-            INSERT_PADDING_WORDS(4);
+            INSERT_PADDING_WORDS(1);
+            DepthView depth_view;
+            INSERT_PADDING_WORDS(2);
             Address depth_htile_data_base;
             INSERT_PADDING_WORDS(2);
             float depth_bounds_min;
@@ -1050,6 +1076,7 @@ static_assert(GFX6_3D_REG_INDEX(cs_program.dim_z) == 0x2E03);
 static_assert(GFX6_3D_REG_INDEX(cs_program.address_lo) == 0x2E0C);
 static_assert(GFX6_3D_REG_INDEX(cs_program.user_data) == 0x2E40);
 static_assert(GFX6_3D_REG_INDEX(depth_render_control) == 0xA000);
+static_assert(GFX6_3D_REG_INDEX(depth_view) == 0xA002);
 static_assert(GFX6_3D_REG_INDEX(depth_htile_data_base) == 0xA005);
 static_assert(GFX6_3D_REG_INDEX(screen_scissor) == 0xA00C);
 static_assert(GFX6_3D_REG_INDEX(depth_buffer.z_info) == 0xA010);

src/video_core/amdgpu/resource.h

@@ -36,6 +36,12 @@ struct Buffer {
     u32 element_size : 2;
     u32 index_stride : 2;
     u32 add_tid_enable : 1;
+    u32 : 6;
+    u32 type : 2; // overlaps with T# type, so should be 0 for buffer
+
+    bool Valid() const {
+        return type == 0u;
+    }
 
     operator bool() const noexcept {
         return base_address != 0;
@@ -106,22 +112,25 @@ constexpr std::string_view NameOf(ImageType type) {
 }
 
 enum class TilingMode : u32 {
-    Depth_MicroTiled = 0x5u,
+    Depth_MacroTiled = 0u,
     Display_Linear = 0x8u,
     Display_MacroTiled = 0xAu,
     Texture_MicroTiled = 0xDu,
+    Texture_MacroTiled = 0xEu,
 };
 
 constexpr std::string_view NameOf(TilingMode type) {
     switch (type) {
-    case TilingMode::Depth_MicroTiled:
-        return "Depth_MicroTiled";
+    case TilingMode::Depth_MacroTiled:
+        return "Depth_MacroTiled";
     case TilingMode::Display_Linear:
         return "Display_Linear";
     case TilingMode::Display_MacroTiled:
         return "Display_MacroTiled";
     case TilingMode::Texture_MicroTiled:
         return "Texture_MicroTiled";
+    case TilingMode::Texture_MacroTiled:
+        return "Texture_MacroTiled";
     default:
         return "Unknown";
     }
@@ -149,7 +158,7 @@ struct Image {
     u64 pow2pad : 1;
     u64 mtype2 : 1;
     u64 atc : 1;
-    u64 type : 4;
+    u64 type : 4; // overlaps with V# type, so shouldn't be 0 for buffer
 
     u64 depth : 13;
     u64 pitch : 14;
@@ -162,6 +171,10 @@ struct Image {
     u64 lod_hw_cnt_en : 1;
     u64 : 43;
 
+    bool Valid() const {
+        return (type & 0x8u) != 0;
+    }
+
     VAddr Address() const {
         return base_address << 8;
     }
@@ -201,17 +214,19 @@ struct Image {
     }
 
     TilingMode GetTilingMode() const {
+        if (tiling_index >= 0 && tiling_index <= 7) {
+            return tiling_index == 5 ? TilingMode::Texture_MicroTiled
+                                     : TilingMode::Depth_MacroTiled;
+        }
+        if (tiling_index == 0x13) {
+            return TilingMode::Texture_MicroTiled;
+        }
         return static_cast<TilingMode>(tiling_index);
     }
 
     bool IsTiled() const {
         return GetTilingMode() != TilingMode::Display_Linear;
     }
-
-    size_t GetSizeAligned() const {
-        // TODO: Derive this properly from tiling params
-        return Pitch() * (height + 1) * NumComponents(GetDataFmt());
-    }
 };
 static_assert(sizeof(Image) == 32); // 256bits