mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-24 12:25:00 +00:00
video_core: Account of runtime state changes when compiling shaders (#575)
* video_core: Compile shader permutations * spirv: Only specific storage image format for atomics * ir: Avoid cube coord patching for storage image * spirv: Fix default attributes * data_share: Add more instructions * video_core: Query storage flag with runtime state * kernel: Use std::list for semaphore * video_core: Use texture buffers for untyped format load/store * buffer_cache: Limit view usage * vk_pipeline_cache: Fix invalid iterator * image_view: Reduce log spam when alpha=1 in storage swizzle * video_core: More features and proper spirv feature detection * video_core: Attempt no2 for specialization * spirv: Remove conflict * vk_shader_cache: Small cleanup
This commit is contained in:
TheTurtle
GitHub
parent
790d19e59b
commit
66e96dd944
43 changed files with 1058 additions and 976 deletions
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@ -325,20 +325,8 @@ Value IREmitter::LoadBuffer(int num_dwords, const Value& handle, const Value& ad
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}
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}
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Value IREmitter::LoadBufferFormat(int num_dwords, const Value& handle, const Value& address,
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BufferInstInfo info) {
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switch (num_dwords) {
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case 1:
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return Inst(Opcode::LoadBufferFormatF32, Flags{info}, handle, address);
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case 2:
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return Inst(Opcode::LoadBufferFormatF32x2, Flags{info}, handle, address);
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case 3:
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return Inst(Opcode::LoadBufferFormatF32x3, Flags{info}, handle, address);
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case 4:
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return Inst(Opcode::LoadBufferFormatF32x4, Flags{info}, handle, address);
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default:
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UNREACHABLE_MSG("Invalid number of dwords {}", num_dwords);
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}
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Value IREmitter::LoadBufferFormat(const Value& handle, const Value& address, BufferInstInfo info) {
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return Inst(Opcode::LoadBufferFormatF32, Flags{info}, handle, address);
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}
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void IREmitter::StoreBuffer(int num_dwords, const Value& handle, const Value& address,
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@ -409,24 +397,9 @@ Value IREmitter::BufferAtomicSwap(const Value& handle, const Value& address, con
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return Inst(Opcode::BufferAtomicSwap32, Flags{info}, handle, address, value);
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}
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void IREmitter::StoreBufferFormat(int num_dwords, const Value& handle, const Value& address,
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const Value& data, BufferInstInfo info) {
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switch (num_dwords) {
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case 1:
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Inst(Opcode::StoreBufferFormatF32, Flags{info}, handle, address, data);
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break;
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case 2:
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Inst(Opcode::StoreBufferFormatF32x2, Flags{info}, handle, address, data);
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break;
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case 3:
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Inst(Opcode::StoreBufferFormatF32x3, Flags{info}, handle, address, data);
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break;
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case 4:
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Inst(Opcode::StoreBufferFormatF32x4, Flags{info}, handle, address, data);
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break;
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default:
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UNREACHABLE_MSG("Invalid number of dwords {}", num_dwords);
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}
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void IREmitter::StoreBufferFormat(const Value& handle, const Value& address, const Value& data,
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BufferInstInfo info) {
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Inst(Opcode::StoreBufferFormatF32, Flags{info}, handle, address, data);
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}
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U32 IREmitter::LaneId() {
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@ -92,12 +92,12 @@ public:
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[[nodiscard]] Value LoadBuffer(int num_dwords, const Value& handle, const Value& address,
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BufferInstInfo info);
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[[nodiscard]] Value LoadBufferFormat(int num_dwords, const Value& handle, const Value& address,
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[[nodiscard]] Value LoadBufferFormat(const Value& handle, const Value& address,
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BufferInstInfo info);
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void StoreBuffer(int num_dwords, const Value& handle, const Value& address, const Value& data,
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BufferInstInfo info);
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void StoreBufferFormat(int num_dwords, const Value& handle, const Value& address,
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const Value& data, BufferInstInfo info);
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void StoreBufferFormat(const Value& handle, const Value& address, const Value& data,
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BufferInstInfo info);
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[[nodiscard]] Value BufferAtomicIAdd(const Value& handle, const Value& address,
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const Value& value, BufferInstInfo info);
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@ -56,9 +56,6 @@ bool Inst::MayHaveSideEffects() const noexcept {
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case Opcode::StoreBufferF32x3:
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case Opcode::StoreBufferF32x4:
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case Opcode::StoreBufferFormatF32:
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case Opcode::StoreBufferFormatF32x2:
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case Opcode::StoreBufferFormatF32x3:
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case Opcode::StoreBufferFormatF32x4:
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case Opcode::StoreBufferU32:
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case Opcode::BufferAtomicIAdd32:
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case Opcode::BufferAtomicSMin32:
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@ -79,19 +79,13 @@ OPCODE(LoadBufferF32, F32, Opaq
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OPCODE(LoadBufferF32x2, F32x2, Opaque, Opaque, )
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OPCODE(LoadBufferF32x3, F32x3, Opaque, Opaque, )
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OPCODE(LoadBufferF32x4, F32x4, Opaque, Opaque, )
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OPCODE(LoadBufferFormatF32, F32, Opaque, Opaque, )
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OPCODE(LoadBufferFormatF32x2, F32x2, Opaque, Opaque, )
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OPCODE(LoadBufferFormatF32x3, F32x3, Opaque, Opaque, )
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OPCODE(LoadBufferFormatF32x4, F32x4, Opaque, Opaque, )
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OPCODE(LoadBufferFormatF32, F32x4, Opaque, Opaque, )
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OPCODE(LoadBufferU32, U32, Opaque, Opaque, )
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OPCODE(StoreBufferF32, Void, Opaque, Opaque, F32, )
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OPCODE(StoreBufferF32x2, Void, Opaque, Opaque, F32x2, )
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OPCODE(StoreBufferF32x3, Void, Opaque, Opaque, F32x3, )
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OPCODE(StoreBufferF32x4, Void, Opaque, Opaque, F32x4, )
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OPCODE(StoreBufferFormatF32, Void, Opaque, Opaque, F32, )
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OPCODE(StoreBufferFormatF32x2, Void, Opaque, Opaque, F32x2, )
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OPCODE(StoreBufferFormatF32x3, Void, Opaque, Opaque, F32x3, )
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OPCODE(StoreBufferFormatF32x4, Void, Opaque, Opaque, F32x4, )
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OPCODE(StoreBufferFormatF32, Void, Opaque, Opaque, F32x4, )
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OPCODE(StoreBufferU32, Void, Opaque, Opaque, U32, )
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// Buffer atomic operations
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@ -3,6 +3,7 @@
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#include <algorithm>
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#include <boost/container/small_vector.hpp>
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#include "common/alignment.h"
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#include "shader_recompiler/ir/basic_block.h"
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#include "shader_recompiler/ir/breadth_first_search.h"
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#include "shader_recompiler/ir/ir_emitter.h"
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@ -45,10 +46,6 @@ bool IsBufferStore(const IR::Inst& inst) {
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case IR::Opcode::StoreBufferF32x2:
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case IR::Opcode::StoreBufferF32x3:
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case IR::Opcode::StoreBufferF32x4:
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case IR::Opcode::StoreBufferFormatF32:
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case IR::Opcode::StoreBufferFormatF32x2:
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case IR::Opcode::StoreBufferFormatF32x3:
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case IR::Opcode::StoreBufferFormatF32x4:
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case IR::Opcode::StoreBufferU32:
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return true;
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default:
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@ -62,10 +59,6 @@ bool IsBufferInstruction(const IR::Inst& inst) {
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case IR::Opcode::LoadBufferF32x2:
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case IR::Opcode::LoadBufferF32x3:
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case IR::Opcode::LoadBufferF32x4:
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case IR::Opcode::LoadBufferFormatF32:
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case IR::Opcode::LoadBufferFormatF32x2:
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case IR::Opcode::LoadBufferFormatF32x3:
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case IR::Opcode::LoadBufferFormatF32x4:
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case IR::Opcode::LoadBufferU32:
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case IR::Opcode::ReadConstBuffer:
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case IR::Opcode::ReadConstBufferU32:
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@ -75,6 +68,11 @@ bool IsBufferInstruction(const IR::Inst& inst) {
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}
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}
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bool IsTextureBufferInstruction(const IR::Inst& inst) {
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return inst.GetOpcode() == IR::Opcode::LoadBufferFormatF32 ||
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inst.GetOpcode() == IR::Opcode::StoreBufferFormatF32;
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}
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static bool UseFP16(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat num_format) {
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switch (num_format) {
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case AmdGpu::NumberFormat::Float:
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@ -100,28 +98,6 @@ static bool UseFP16(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat num_for
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IR::Type BufferDataType(const IR::Inst& inst, AmdGpu::NumberFormat num_format) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::LoadBufferFormatF32:
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case IR::Opcode::LoadBufferFormatF32x2:
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case IR::Opcode::LoadBufferFormatF32x3:
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case IR::Opcode::LoadBufferFormatF32x4:
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case IR::Opcode::StoreBufferFormatF32:
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case IR::Opcode::StoreBufferFormatF32x2:
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case IR::Opcode::StoreBufferFormatF32x3:
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case IR::Opcode::StoreBufferFormatF32x4:
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switch (num_format) {
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case AmdGpu::NumberFormat::Unorm:
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case AmdGpu::NumberFormat::Snorm:
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case AmdGpu::NumberFormat::Uscaled:
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case AmdGpu::NumberFormat::Sscaled:
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case AmdGpu::NumberFormat::Uint:
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case AmdGpu::NumberFormat::Sint:
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case AmdGpu::NumberFormat::SnormNz:
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return IR::Type::U32;
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case AmdGpu::NumberFormat::Float:
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return IR::Type::F32;
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default:
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UNREACHABLE();
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}
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case IR::Opcode::LoadBufferF32:
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case IR::Opcode::LoadBufferF32x2:
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case IR::Opcode::LoadBufferF32x3:
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@ -143,20 +119,8 @@ IR::Type BufferDataType(const IR::Inst& inst, AmdGpu::NumberFormat num_format) {
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}
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}
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bool IsImageInstruction(const IR::Inst& inst) {
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bool IsImageAtomicInstruction(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::ImageSampleExplicitLod:
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case IR::Opcode::ImageSampleImplicitLod:
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case IR::Opcode::ImageSampleDrefExplicitLod:
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case IR::Opcode::ImageSampleDrefImplicitLod:
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case IR::Opcode::ImageFetch:
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case IR::Opcode::ImageGather:
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case IR::Opcode::ImageGatherDref:
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case IR::Opcode::ImageQueryDimensions:
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case IR::Opcode::ImageQueryLod:
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case IR::Opcode::ImageGradient:
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case IR::Opcode::ImageRead:
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case IR::Opcode::ImageWrite:
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case IR::Opcode::ImageAtomicIAdd32:
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case IR::Opcode::ImageAtomicSMin32:
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case IR::Opcode::ImageAtomicUMin32:
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@ -178,20 +142,27 @@ bool IsImageStorageInstruction(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::ImageWrite:
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case IR::Opcode::ImageRead:
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case IR::Opcode::ImageAtomicIAdd32:
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case IR::Opcode::ImageAtomicSMin32:
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case IR::Opcode::ImageAtomicUMin32:
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case IR::Opcode::ImageAtomicSMax32:
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case IR::Opcode::ImageAtomicUMax32:
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case IR::Opcode::ImageAtomicInc32:
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case IR::Opcode::ImageAtomicDec32:
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case IR::Opcode::ImageAtomicAnd32:
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case IR::Opcode::ImageAtomicOr32:
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case IR::Opcode::ImageAtomicXor32:
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case IR::Opcode::ImageAtomicExchange32:
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return true;
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default:
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return false;
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return IsImageAtomicInstruction(inst);
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}
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}
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bool IsImageInstruction(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::ImageSampleExplicitLod:
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case IR::Opcode::ImageSampleImplicitLod:
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case IR::Opcode::ImageSampleDrefExplicitLod:
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case IR::Opcode::ImageSampleDrefImplicitLod:
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case IR::Opcode::ImageFetch:
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case IR::Opcode::ImageGather:
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case IR::Opcode::ImageGatherDref:
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case IR::Opcode::ImageQueryDimensions:
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case IR::Opcode::ImageQueryLod:
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case IR::Opcode::ImageGradient:
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return true;
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default:
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return IsImageStorageInstruction(inst);
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}
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}
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@ -214,7 +185,8 @@ u32 ImageOffsetArgumentPosition(const IR::Inst& inst) {
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class Descriptors {
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public:
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explicit Descriptors(Info& info_)
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: info{info_}, buffer_resources{info_.buffers}, image_resources{info_.images},
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: info{info_}, buffer_resources{info_.buffers},
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texture_buffer_resources{info_.texture_buffers}, image_resources{info_.images},
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sampler_resources{info_.samplers} {}
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u32 Add(const BufferResource& desc) {
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@ -224,13 +196,21 @@ public:
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desc.inline_cbuf == existing.inline_cbuf;
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})};
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auto& buffer = buffer_resources[index];
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ASSERT(buffer.length == desc.length);
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buffer.is_storage |= desc.is_storage;
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buffer.used_types |= desc.used_types;
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buffer.is_written |= desc.is_written;
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return index;
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}
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u32 Add(const TextureBufferResource& desc) {
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const u32 index{Add(texture_buffer_resources, desc, [&desc](const auto& existing) {
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return desc.sgpr_base == existing.sgpr_base &&
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desc.dword_offset == existing.dword_offset;
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})};
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auto& buffer = texture_buffer_resources[index];
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buffer.is_written |= desc.is_written;
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return index;
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}
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u32 Add(const ImageResource& desc) {
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const u32 index{Add(image_resources, desc, [&desc](const auto& existing) {
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return desc.sgpr_base == existing.sgpr_base &&
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@ -247,7 +227,7 @@ public:
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return true;
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}
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// Samplers with different bindings might still be the same.
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return existing.GetSsharp(info) == desc.GetSsharp(info);
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return existing.GetSharp(info) == desc.GetSharp(info);
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})};
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return index;
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}
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@ -265,6 +245,7 @@ private:
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const Info& info;
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BufferResourceList& buffer_resources;
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TextureBufferResourceList& texture_buffer_resources;
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ImageResourceList& image_resources;
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SamplerResourceList& sampler_resources;
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};
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@ -361,33 +342,6 @@ SharpLocation TrackSharp(const IR::Inst* inst) {
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};
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}
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static constexpr size_t MaxUboSize = 65536;
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static bool IsLoadBufferFormat(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::LoadBufferFormatF32:
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case IR::Opcode::LoadBufferFormatF32x2:
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case IR::Opcode::LoadBufferFormatF32x3:
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case IR::Opcode::LoadBufferFormatF32x4:
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return true;
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default:
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return false;
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}
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}
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static u32 BufferLength(const AmdGpu::Buffer& buffer) {
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const auto stride = buffer.GetStride();
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if (stride < sizeof(f32)) {
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ASSERT(sizeof(f32) % stride == 0);
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return (((buffer.num_records - 1) / sizeof(f32)) + 1) * stride;
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} else if (stride == sizeof(f32)) {
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return buffer.num_records;
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} else {
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ASSERT(stride % sizeof(f32) == 0);
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return buffer.num_records * (stride / sizeof(f32));
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}
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}
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s32 TryHandleInlineCbuf(IR::Inst& inst, Info& info, Descriptors& descriptors,
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AmdGpu::Buffer& cbuf) {
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@ -414,10 +368,8 @@ s32 TryHandleInlineCbuf(IR::Inst& inst, Info& info, Descriptors& descriptors,
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return descriptors.Add(BufferResource{
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.sgpr_base = std::numeric_limits<u32>::max(),
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.dword_offset = 0,
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.length = BufferLength(cbuf),
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.used_types = BufferDataType(inst, cbuf.GetNumberFmt()),
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.inline_cbuf = cbuf,
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.is_storage = IsBufferStore(inst) || cbuf.GetSize() > MaxUboSize,
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});
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}
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@ -429,28 +381,17 @@ void PatchBufferInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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IR::Inst* handle = inst.Arg(0).InstRecursive();
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IR::Inst* producer = handle->Arg(0).InstRecursive();
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const auto sharp = TrackSharp(producer);
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const bool is_store = IsBufferStore(inst);
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buffer = info.ReadUd<AmdGpu::Buffer>(sharp.sgpr_base, sharp.dword_offset);
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binding = descriptors.Add(BufferResource{
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.sgpr_base = sharp.sgpr_base,
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.dword_offset = sharp.dword_offset,
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.length = BufferLength(buffer),
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.used_types = BufferDataType(inst, buffer.GetNumberFmt()),
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.is_storage = is_store || buffer.GetSize() > MaxUboSize,
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.is_written = is_store,
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.is_written = IsBufferStore(inst),
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});
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}
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// Update buffer descriptor format.
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const auto inst_info = inst.Flags<IR::BufferInstInfo>();
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auto& buffer_desc = info.buffers[binding];
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if (inst_info.is_typed) {
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buffer_desc.dfmt = inst_info.dmft;
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buffer_desc.nfmt = inst_info.nfmt;
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} else {
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buffer_desc.dfmt = buffer.GetDataFmt();
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buffer_desc.nfmt = buffer.GetNumberFmt();
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}
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// Replace handle with binding index in buffer resource list.
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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@ -463,20 +404,7 @@ void PatchBufferInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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return;
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}
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if (IsLoadBufferFormat(inst)) {
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if (UseFP16(buffer.GetDataFmt(), buffer.GetNumberFmt())) {
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info.uses_fp16 = true;
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}
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} else {
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const u32 stride = buffer.GetStride();
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if (stride < 4) {
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LOG_WARNING(Render_Vulkan,
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"non-formatting load_buffer_* is not implemented for stride {}", stride);
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}
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}
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// Compute address of the buffer using the stride.
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// Todo: What if buffer is rebound with different stride?
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IR::U32 address = ir.Imm32(inst_info.inst_offset.Value());
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if (inst_info.index_enable) {
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const IR::U32 index = inst_info.offset_enable ? IR::U32{ir.CompositeExtract(inst.Arg(1), 0)}
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@ -491,8 +419,31 @@ void PatchBufferInstruction(IR::Block& block, IR::Inst& inst, Info& info,
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inst.SetArg(1, address);
|
||||
}
|
||||
|
||||
void PatchTextureBufferInstruction(IR::Block& block, IR::Inst& inst, Info& info,
|
||||
Descriptors& descriptors) {
|
||||
const IR::Inst* handle = inst.Arg(0).InstRecursive();
|
||||
const IR::Inst* producer = handle->Arg(0).InstRecursive();
|
||||
const auto sharp = TrackSharp(producer);
|
||||
const auto buffer = info.ReadUd<AmdGpu::Buffer>(sharp.sgpr_base, sharp.dword_offset);
|
||||
const s32 binding = descriptors.Add(TextureBufferResource{
|
||||
.sgpr_base = sharp.sgpr_base,
|
||||
.dword_offset = sharp.dword_offset,
|
||||
.nfmt = buffer.GetNumberFmt(),
|
||||
.is_written = inst.GetOpcode() == IR::Opcode::StoreBufferFormatF32,
|
||||
});
|
||||
|
||||
// Replace handle with binding index in texture buffer resource list.
|
||||
IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
|
||||
inst.SetArg(0, ir.Imm32(binding));
|
||||
ASSERT(!buffer.swizzle_enable && !buffer.add_tid_enable);
|
||||
}
|
||||
|
||||
IR::Value PatchCubeCoord(IR::IREmitter& ir, const IR::Value& s, const IR::Value& t,
|
||||
const IR::Value& z) {
|
||||
const IR::Value& z, bool is_storage) {
|
||||
// When cubemap is written with imageStore it is treated like 2DArray.
|
||||
if (is_storage) {
|
||||
return ir.CompositeConstruct(s, t, z);
|
||||
}
|
||||
// We need to fix x and y coordinate,
|
||||
// because the s and t coordinate will be scaled and plus 1.5 by v_madak_f32.
|
||||
// We already force the scale value to be 1.0 when handling v_cubema_f32,
|
||||
|
|
@ -530,13 +481,15 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
|
|||
return;
|
||||
}
|
||||
ASSERT(image.GetType() != AmdGpu::ImageType::Invalid);
|
||||
const bool is_storage = IsImageStorageInstruction(inst);
|
||||
u32 image_binding = descriptors.Add(ImageResource{
|
||||
.sgpr_base = tsharp.sgpr_base,
|
||||
.dword_offset = tsharp.dword_offset,
|
||||
.type = image.GetType(),
|
||||
.nfmt = static_cast<AmdGpu::NumberFormat>(image.GetNumberFmt()),
|
||||
.is_storage = IsImageStorageInstruction(inst),
|
||||
.is_storage = is_storage,
|
||||
.is_depth = bool(inst_info.is_depth),
|
||||
.is_atomic = IsImageAtomicInstruction(inst),
|
||||
});
|
||||
|
||||
// Read sampler sharp. This doesn't exist for IMAGE_LOAD/IMAGE_STORE instructions
|
||||
|
|
@ -593,7 +546,8 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
|
|||
case AmdGpu::ImageType::Color3D: // x, y, z
|
||||
return {ir.CompositeConstruct(body->Arg(0), body->Arg(1), body->Arg(2)), body->Arg(3)};
|
||||
case AmdGpu::ImageType::Cube: // x, y, face
|
||||
return {PatchCubeCoord(ir, body->Arg(0), body->Arg(1), body->Arg(2)), body->Arg(3)};
|
||||
return {PatchCubeCoord(ir, body->Arg(0), body->Arg(1), body->Arg(2), is_storage),
|
||||
body->Arg(3)};
|
||||
default:
|
||||
UNREACHABLE_MSG("Unknown image type {}", image.GetType());
|
||||
}
|
||||
|
|
@ -668,6 +622,10 @@ void ResourceTrackingPass(IR::Program& program) {
|
|||
PatchBufferInstruction(*block, inst, info, descriptors);
|
||||
continue;
|
||||
}
|
||||
if (IsTextureBufferInstruction(inst)) {
|
||||
PatchTextureBufferInstruction(*block, inst, info, descriptors);
|
||||
continue;
|
||||
}
|
||||
if (IsImageInstruction(inst)) {
|
||||
PatchImageInstruction(*block, inst, info, descriptors);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,6 +29,12 @@ void Visit(Info& info, IR::Inst& inst) {
|
|||
case IR::Opcode::ImageWrite:
|
||||
info.has_storage_images = true;
|
||||
break;
|
||||
case IR::Opcode::LoadBufferFormatF32:
|
||||
info.has_texel_buffers = true;
|
||||
break;
|
||||
case IR::Opcode::StoreBufferFormatF32:
|
||||
info.has_image_buffers = true;
|
||||
break;
|
||||
case IR::Opcode::QuadShuffle:
|
||||
info.uses_group_quad = true;
|
||||
break;
|
||||
|
|
@ -44,6 +50,9 @@ void Visit(Info& info, IR::Inst& inst) {
|
|||
case IR::Opcode::ImageQueryLod:
|
||||
info.has_image_query = true;
|
||||
break;
|
||||
case IR::Opcode::LaneId:
|
||||
info.uses_lane_id = true;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,11 +12,13 @@
|
|||
namespace Shader::IR {
|
||||
|
||||
struct Program {
|
||||
explicit Program(Info& info_) : info{info_} {}
|
||||
|
||||
AbstractSyntaxList syntax_list;
|
||||
BlockList blocks;
|
||||
BlockList post_order_blocks;
|
||||
std::vector<Gcn::GcnInst> ins_list;
|
||||
Info info;
|
||||
Info& info;
|
||||
};
|
||||
|
||||
[[nodiscard]] std::string DumpProgram(const Program& program);
|
||||
|
|
|
|||
|
|
@ -66,9 +66,6 @@ union BufferInstInfo {
|
|||
BitField<0, 1, u32> index_enable;
|
||||
BitField<1, 1, u32> offset_enable;
|
||||
BitField<2, 12, u32> inst_offset;
|
||||
BitField<14, 4, AmdGpu::DataFormat> dmft;
|
||||
BitField<18, 3, AmdGpu::NumberFormat> nfmt;
|
||||
BitField<21, 1, u32> is_typed;
|
||||
};
|
||||
|
||||
enum class ScalarReg : u32 {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue