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https://github.com/shadps4-emu/shadPS4.git
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64 bits OP, impl V_ADDC_U32 & V_MAD_U64_U32 (#310)
* impl V_ADDC_U32 & V_MAD_U64_U32 * shader recompiler: add 64 bits version to get register / GetSrc * fix V_ADDC_U32 carry * shader recompiler: removed automatic conversion to force_flt in GetSRc * shader recompiler: auto cast between u32 and u64 during ssa pass * shader recompiler: fix SetVectorReg64 & standardize switches-case * shader translate: fix overflow detection in V_ADD_I32 use vcc lo instead of vcc thread bit * shader recompiler: more 64-bit work - removed bit_size parameter from Get[Scalar/Vector]Register - add BitwiseOr64 - add SetDst64 as a replacement for SetScalarReg64 & SetVectorReg64 - add GetSrc64 for 64-bit value * shader recompiler: add V_MAD_U64_U32 vcc output - add V_MAD_U64_U32 vcc output - ILessThan for 64-bits * shader recompiler: removed unnecessary changes & missing consts * shader_recompiler: Add s64 type in constant propagation
This commit is contained in:
Vinicius Rangel
GitHub
parent
d84b4adc83
commit
680192a0c4
12 changed files with 361 additions and 40 deletions
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@ -76,21 +76,21 @@ void Translator::EmitPrologue() {
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}
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}
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template <>
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IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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// Input modifiers work on float values.
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force_flt |= operand.input_modifier.abs | operand.input_modifier.neg;
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IR::U32F32 value{};
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const bool is_float = operand.type == ScalarType::Float32 || force_flt;
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (operand.type == ScalarType::Float32 || force_flt) {
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if (is_float) {
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value = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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} else {
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value = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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}
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break;
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case OperandField::VectorGPR:
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if (operand.type == ScalarType::Float32 || force_flt) {
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if (is_float) {
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value = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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} else {
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value = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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@ -164,15 +164,160 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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UNREACHABLE();
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}
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(value);
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if (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(value);
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(value);
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}
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}
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return value;
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}
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template <>
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IR::U32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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return GetSrc<IR::U32F32>(operand, force_flt);
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}
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template <>
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IR::F32 Translator::GetSrc(const InstOperand& operand, bool) {
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return GetSrc<IR::U32F32>(operand, true);
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}
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template <>
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IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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IR::Value value_hi{};
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IR::Value value_lo{};
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bool immediate = false;
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const bool is_float = operand.type == ScalarType::Float64 || force_flt;
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (is_float) {
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value_lo = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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value_hi = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code + 1));
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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value_lo = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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value_hi = ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code + 1));
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} else {
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UNREACHABLE();
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}
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break;
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case OperandField::VectorGPR:
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if (is_float) {
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value_lo = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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value_hi = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code + 1));
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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value_lo = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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value_hi = ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code + 1));
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} else {
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UNREACHABLE();
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}
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break;
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case OperandField::ConstZero:
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immediate = true;
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if (force_flt) {
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value_lo = ir.Imm64(0.0);
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} else {
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value_lo = ir.Imm64(u64(0U));
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}
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break;
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case OperandField::SignedConstIntPos:
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ASSERT(!force_flt);
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immediate = true;
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value_lo = ir.Imm64(s64(operand.code) - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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ASSERT(!force_flt);
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immediate = true;
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value_lo = ir.Imm64(-s64(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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immediate = true;
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if (force_flt) {
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UNREACHABLE(); // There is a literal double?
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} else {
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value_lo = ir.Imm64(u64(operand.code));
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}
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break;
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case OperandField::ConstFloatPos_1_0:
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immediate = true;
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if (force_flt) {
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value_lo = ir.Imm64(1.0);
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} else {
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value_lo = ir.Imm64(std::bit_cast<u64>(f64(1.0)));
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}
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break;
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case OperandField::ConstFloatPos_0_5:
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immediate = true;
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value_lo = ir.Imm64(0.5);
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break;
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case OperandField::ConstFloatPos_2_0:
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immediate = true;
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value_lo = ir.Imm64(2.0);
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break;
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case OperandField::ConstFloatPos_4_0:
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immediate = true;
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value_lo = ir.Imm64(4.0);
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break;
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case OperandField::ConstFloatNeg_0_5:
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immediate = true;
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value_lo = ir.Imm64(-0.5);
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break;
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case OperandField::ConstFloatNeg_1_0:
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immediate = true;
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value_lo = ir.Imm64(-1.0);
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break;
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case OperandField::ConstFloatNeg_2_0:
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immediate = true;
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value_lo = ir.Imm64(-2.0);
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break;
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case OperandField::ConstFloatNeg_4_0:
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immediate = true;
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value_lo = ir.Imm64(-4.0);
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break;
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case OperandField::VccLo: {
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value_lo = ir.GetVccLo();
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value_hi = ir.GetVccHi();
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} break;
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case OperandField::VccHi:
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UNREACHABLE();
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default:
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UNREACHABLE();
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}
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IR::Value value;
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if (immediate) {
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value = value_lo;
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} else if (is_float) {
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throw NotImplementedException("required OpPackDouble2x32 implementation");
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} else {
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IR::Value packed = ir.CompositeConstruct(value_lo, value_hi);
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value = ir.PackUint2x32(packed);
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}
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if (is_float) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(IR::F32F64(value));
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}
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if (operand.input_modifier.neg) {
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value = ir.FPNeg(IR::F32F64(value));
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}
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}
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return IR::U64F64(value);
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}
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template <>
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IR::U64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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return GetSrc64<IR::U64F64>(operand, force_flt);
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}
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template <>
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IR::F64 Translator::GetSrc64(const InstOperand& operand, bool) {
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return GetSrc64<IR::U64F64>(operand, true);
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}
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void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
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IR::U32F32 result = value;
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if (operand.output_modifier.multiplier != 0.f) {
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@ -197,6 +342,43 @@ void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
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}
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}
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void Translator::SetDst64(const InstOperand& operand, const IR::U64F64& value_raw) {
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IR::U64F64 value_untyped = value_raw;
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const bool is_float = value_raw.Type() == IR::Type::F64 || value_raw.Type() == IR::Type::F32;
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if (is_float) {
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if (operand.output_modifier.multiplier != 0.f) {
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value_untyped =
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ir.FPMul(value_untyped, ir.Imm64(f64(operand.output_modifier.multiplier)));
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}
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if (operand.output_modifier.clamp) {
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value_untyped = ir.FPSaturate(value_raw);
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}
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}
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const IR::U64 value =
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is_float ? ir.BitCast<IR::U64>(IR::F64{value_untyped}) : IR::U64{value_untyped};
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const IR::Value unpacked{ir.UnpackUint2x32(value)};
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const IR::U32 lo{ir.CompositeExtract(unpacked, 0U)};
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const IR::U32 hi{ir.CompositeExtract(unpacked, 1U)};
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switch (operand.field) {
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case OperandField::ScalarGPR:
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ir.SetScalarReg(IR::ScalarReg(operand.code + 1), hi);
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return ir.SetScalarReg(IR::ScalarReg(operand.code), lo);
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case OperandField::VectorGPR:
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ir.SetVectorReg(IR::VectorReg(operand.code + 1), hi);
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return ir.SetVectorReg(IR::VectorReg(operand.code), lo);
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case OperandField::VccLo:
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UNREACHABLE();
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case OperandField::VccHi:
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UNREACHABLE();
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case OperandField::M0:
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break;
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default:
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UNREACHABLE();
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}
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}
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void Translator::EmitFetch(const GcnInst& inst) {
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// Read the pointer to the fetch shader assembly.
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const u32 sgpr_base = inst.src[0].code;
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@ -320,6 +502,9 @@ void Translate(IR::Block* block, u32 block_base, std::span<const GcnInst> inst_l
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case Opcode::V_ADD_I32:
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translator.V_ADD_I32(inst);
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break;
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case Opcode::V_ADDC_U32:
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translator.V_ADDC_U32(inst);
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break;
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case Opcode::V_CVT_F32_I32:
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translator.V_CVT_F32_I32(inst);
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break;
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@ -470,6 +655,9 @@ void Translate(IR::Block* block, u32 block_base, std::span<const GcnInst> inst_l
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case Opcode::IMAGE_LOAD:
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translator.IMAGE_LOAD(false, inst);
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break;
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case Opcode::V_MAD_U64_U32:
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translator.V_MAD_U64_U32(inst);
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break;
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case Opcode::V_CMP_GE_I32:
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translator.V_CMP_U32(ConditionOp::GE, true, false, inst);
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break;
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