mirror of
https://github.com/shadps4-emu/shadPS4.git
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64 bits OP, impl V_ADDC_U32 & V_MAD_U64_U32 (#310)
* impl V_ADDC_U32 & V_MAD_U64_U32 * shader recompiler: add 64 bits version to get register / GetSrc * fix V_ADDC_U32 carry * shader recompiler: removed automatic conversion to force_flt in GetSRc * shader recompiler: auto cast between u32 and u64 during ssa pass * shader recompiler: fix SetVectorReg64 & standardize switches-case * shader translate: fix overflow detection in V_ADD_I32 use vcc lo instead of vcc thread bit * shader recompiler: more 64-bit work - removed bit_size parameter from Get[Scalar/Vector]Register - add BitwiseOr64 - add SetDst64 as a replacement for SetScalarReg64 & SetVectorReg64 - add GetSrc64 for 64-bit value * shader recompiler: add V_MAD_U64_U32 vcc output - add V_MAD_U64_U32 vcc output - ILessThan for 64-bits * shader recompiler: removed unnecessary changes & missing consts * shader_recompiler: Add s64 type in constant propagation
This commit is contained in:
Vinicius Rangel
GitHub
parent
d84b4adc83
commit
680192a0c4
12 changed files with 361 additions and 40 deletions
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@ -964,8 +964,18 @@ IR::Value IREmitter::IMulExt(const U32& a, const U32& b, bool is_signed) {
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return Inst(is_signed ? Opcode::SMulExt : Opcode::UMulExt, a, b);
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}
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U32 IREmitter::IMul(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::IMul32, a, b);
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U32U64 IREmitter::IMul(const U32U64& a, const U32U64& b) {
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if (a.Type() != b.Type()) {
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UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type());
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}
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switch (a.Type()) {
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case Type::U32:
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return Inst<U32>(Opcode::IMul32, a, b);
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case Type::U64:
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return Inst<U64>(Opcode::IMul64, a, b);
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default:
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ThrowInvalidType(a.Type());
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}
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}
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U32 IREmitter::IDiv(const U32& a, const U32& b, bool is_signed) {
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@ -1024,8 +1034,18 @@ U32 IREmitter::BitwiseAnd(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::BitwiseAnd32, a, b);
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}
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U32 IREmitter::BitwiseOr(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::BitwiseOr32, a, b);
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U32U64 IREmitter::BitwiseOr(const U32U64& a, const U32U64& b) {
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if (a.Type() != b.Type()) {
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UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type());
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}
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switch (a.Type()) {
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case Type::U32:
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return Inst<U32>(Opcode::BitwiseOr32, a, b);
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case Type::U64:
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return Inst<U64>(Opcode::BitwiseOr64, a, b);
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default:
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ThrowInvalidType(a.Type());
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}
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}
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U32 IREmitter::BitwiseXor(const U32& a, const U32& b) {
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@ -1095,8 +1115,18 @@ U32 IREmitter::UClamp(const U32& value, const U32& min, const U32& max) {
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return Inst<U32>(Opcode::UClamp32, value, min, max);
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}
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U1 IREmitter::ILessThan(const U32& lhs, const U32& rhs, bool is_signed) {
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return Inst<U1>(is_signed ? Opcode::SLessThan : Opcode::ULessThan, lhs, rhs);
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U1 IREmitter::ILessThan(const U32U64& lhs, const U32U64& rhs, bool is_signed) {
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if (lhs.Type() != rhs.Type()) {
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UNREACHABLE_MSG("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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}
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switch (lhs.Type()) {
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case Type::U32:
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return Inst<U1>(is_signed ? Opcode::SLessThan32 : Opcode::ULessThan32, lhs, rhs);
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case Type::U64:
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return Inst<U1>(is_signed ? Opcode::SLessThan64 : Opcode::ULessThan64, lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type());
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}
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}
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U1 IREmitter::IEqual(const U32U64& lhs, const U32U64& rhs) {
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@ -1155,8 +1185,9 @@ U32U64 IREmitter::ConvertFToS(size_t bitsize, const F32F64& value) {
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ThrowInvalidType(value.Type());
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}
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default:
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UNREACHABLE_MSG("Invalid destination bitsize {}", bitsize);
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break;
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}
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throw NotImplementedException("Invalid destination bitsize {}", bitsize);
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}
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U32U64 IREmitter::ConvertFToU(size_t bitsize, const F32F64& value) {
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@ -1183,13 +1214,17 @@ F32F64 IREmitter::ConvertSToF(size_t dest_bitsize, size_t src_bitsize, const Val
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switch (src_bitsize) {
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case 32:
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return Inst<F32>(Opcode::ConvertF32S32, value);
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default:
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break;
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}
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break;
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case 64:
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switch (src_bitsize) {
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case 32:
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return Inst<F64>(Opcode::ConvertF64S32, value);
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default:
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break;
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}
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default:
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break;
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}
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UNREACHABLE_MSG("Invalid bit size combination dst={} src={}", dest_bitsize, src_bitsize);
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@ -1203,13 +1238,17 @@ F32F64 IREmitter::ConvertUToF(size_t dest_bitsize, size_t src_bitsize, const Val
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return Inst<F32>(Opcode::ConvertF32U16, value);
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case 32:
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return Inst<F32>(Opcode::ConvertF32U32, value);
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default:
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break;
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}
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break;
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case 64:
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switch (src_bitsize) {
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case 32:
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return Inst<F64>(Opcode::ConvertF64U32, value);
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default:
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break;
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}
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default:
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break;
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}
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UNREACHABLE_MSG("Invalid bit size combination dst={} src={}", dest_bitsize, src_bitsize);
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@ -1227,7 +1266,11 @@ U16U32U64 IREmitter::UConvert(size_t result_bitsize, const U16U32U64& value) {
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switch (value.Type()) {
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case Type::U32:
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return Inst<U16>(Opcode::ConvertU16U32, value);
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default:
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break;
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}
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default:
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break;
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}
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throw NotImplementedException("Conversion from {} to {} bits", value.Type(), result_bitsize);
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}
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@ -1238,13 +1281,17 @@ F16F32F64 IREmitter::FPConvert(size_t result_bitsize, const F16F32F64& value) {
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switch (value.Type()) {
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case Type::F32:
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return Inst<F16>(Opcode::ConvertF16F32, value);
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default:
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break;
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}
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break;
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case 32:
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switch (value.Type()) {
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case Type::F16:
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return Inst<F32>(Opcode::ConvertF32F16, value);
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default:
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break;
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}
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default:
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break;
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}
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throw NotImplementedException("Conversion from {} to {} bits", value.Type(), result_bitsize);
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@ -159,7 +159,7 @@ public:
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[[nodiscard]] Value IAddCary(const U32& a, const U32& b);
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[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
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[[nodiscard]] Value IMulExt(const U32& a, const U32& b, bool is_signed = false);
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[[nodiscard]] U32 IMul(const U32& a, const U32& b);
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[[nodiscard]] U32U64 IMul(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32 IDiv(const U32& a, const U32& b, bool is_signed = false);
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[[nodiscard]] U32U64 INeg(const U32U64& value);
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[[nodiscard]] U32 IAbs(const U32& value);
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@ -167,7 +167,7 @@ public:
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[[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift);
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[[nodiscard]] U32U64 ShiftRightArithmetic(const U32U64& base, const U32& shift);
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[[nodiscard]] U32 BitwiseAnd(const U32& a, const U32& b);
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[[nodiscard]] U32 BitwiseOr(const U32& a, const U32& b);
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[[nodiscard]] U32U64 BitwiseOr(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32 BitwiseXor(const U32& a, const U32& b);
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[[nodiscard]] U32 BitFieldInsert(const U32& base, const U32& insert, const U32& offset,
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const U32& count);
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@ -188,7 +188,7 @@ public:
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[[nodiscard]] U32 SClamp(const U32& value, const U32& min, const U32& max);
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[[nodiscard]] U32 UClamp(const U32& value, const U32& min, const U32& max);
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[[nodiscard]] U1 ILessThan(const U32& lhs, const U32& rhs, bool is_signed);
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[[nodiscard]] U1 ILessThan(const U32U64& lhs, const U32U64& rhs, bool is_signed);
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[[nodiscard]] U1 IEqual(const U32U64& lhs, const U32U64& rhs);
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[[nodiscard]] U1 ILessThanEqual(const U32& lhs, const U32& rhs, bool is_signed);
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[[nodiscard]] U1 IGreaterThan(const U32& lhs, const U32& rhs, bool is_signed);
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@ -227,6 +227,7 @@ OPCODE(IAddCary32, U32x2, U32,
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OPCODE(ISub32, U32, U32, U32, )
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OPCODE(ISub64, U64, U64, U64, )
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OPCODE(IMul32, U32, U32, U32, )
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OPCODE(IMul64, U64, U64, U64, )
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OPCODE(SMulExt, U32x2, U32, U32, )
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OPCODE(UMulExt, U32x2, U32, U32, )
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OPCODE(SDiv32, U32, U32, U32, )
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@ -242,6 +243,7 @@ OPCODE(ShiftRightArithmetic32, U32, U32,
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OPCODE(ShiftRightArithmetic64, U64, U64, U32, )
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OPCODE(BitwiseAnd32, U32, U32, U32, )
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OPCODE(BitwiseOr32, U32, U32, U32, )
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OPCODE(BitwiseOr64, U64, U64, U64, )
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OPCODE(BitwiseXor32, U32, U32, U32, )
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OPCODE(BitFieldInsert, U32, U32, U32, U32, U32, )
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OPCODE(BitFieldSExtract, U32, U32, U32, U32, )
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@ -258,8 +260,10 @@ OPCODE(SMax32, U32, U32,
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OPCODE(UMax32, U32, U32, U32, )
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OPCODE(SClamp32, U32, U32, U32, U32, )
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OPCODE(UClamp32, U32, U32, U32, U32, )
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OPCODE(SLessThan, U1, U32, U32, )
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OPCODE(ULessThan, U1, U32, U32, )
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OPCODE(SLessThan32, U1, U32, U32, )
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OPCODE(SLessThan64, U1, U64, U64, )
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OPCODE(ULessThan32, U1, U32, U32, )
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OPCODE(ULessThan64, U1, U64, U64, )
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OPCODE(IEqual, U1, U32, U32, )
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OPCODE(SLessThanEqual, U1, U32, U32, )
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OPCODE(ULessThanEqual, U1, U32, U32, )
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@ -21,6 +21,8 @@ template <typename T>
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return value.F32();
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} else if constexpr (std::is_same_v<T, u64>) {
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return value.U64();
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} else if constexpr (std::is_same_v<T, s64>) {
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return static_cast<s64>(value.U64());
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}
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}
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@ -281,12 +283,18 @@ void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
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return FoldLogicalOr(inst);
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case IR::Opcode::LogicalNot:
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return FoldLogicalNot(inst);
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case IR::Opcode::SLessThan:
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case IR::Opcode::SLessThan32:
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FoldWhenAllImmediates(inst, [](s32 a, s32 b) { return a < b; });
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return;
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case IR::Opcode::ULessThan:
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case IR::Opcode::SLessThan64:
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FoldWhenAllImmediates(inst, [](s64 a, s64 b) { return a < b; });
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return;
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case IR::Opcode::ULessThan32:
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FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a < b; });
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return;
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case IR::Opcode::ULessThan64:
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FoldWhenAllImmediates(inst, [](u64 a, u64 b) { return a < b; });
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return;
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case IR::Opcode::SLessThanEqual:
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FoldWhenAllImmediates(inst, [](s32 a, s32 b) { return a <= b; });
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return;
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@ -348,13 +348,15 @@ void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
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case IR::Opcode::GetThreadBitScalarReg:
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case IR::Opcode::GetScalarRegister: {
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const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
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inst.ReplaceUsesWith(
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pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg));
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const bool thread_bit = opcode == IR::Opcode::GetThreadBitScalarReg;
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const IR::Value value = pass.ReadVariable(reg, block, thread_bit);
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inst.ReplaceUsesWith(value);
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break;
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}
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case IR::Opcode::GetVectorRegister: {
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const IR::VectorReg reg{inst.Arg(0).VectorReg()};
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inst.ReplaceUsesWith(pass.ReadVariable(reg, block));
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const IR::Value value = pass.ReadVariable(reg, block);
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inst.ReplaceUsesWith(value);
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break;
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}
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case IR::Opcode::GetGotoVariable:
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@ -220,6 +220,7 @@ using F16 = TypedValue<Type::F16>;
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using F32 = TypedValue<Type::F32>;
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using F64 = TypedValue<Type::F64>;
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using U32F32 = TypedValue<Type::U32 | Type::F32>;
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using U64F64 = TypedValue<Type::U64 | Type::F64>;
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using U32U64 = TypedValue<Type::U32 | Type::U64>;
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using U16U32U64 = TypedValue<Type::U16 | Type::U32 | Type::U64>;
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using F32F64 = TypedValue<Type::F32 | Type::F64>;
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