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https://github.com/shadps4-emu/shadPS4.git
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shader_recompiler: Implement most integer image atomics, workgroup barriers and shared memory load/store (#231)
* shader_recompiler: Add LDEXP * shader_recompiler: Add most image integer atomic ops * shader_recompiler: Implement shared memory load/store * shader_recompiler: More image atomics * externals: Update sirit * clang format * cmake: Add missing files * shader_recompiler: Fix some atomic bugs * shader_recompiler: Vs outputs * shader_recompiler: Shared mem has side-effects, fix format component order * shader_recompiler: Inline constant buffer impl * video_core: Fix regressions * Work * Fixup a few things
This commit is contained in:
TheTurtle
GitHub
parent
af3bbc33e9
commit
6ceab6dfac
69 changed files with 1597 additions and 310 deletions
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@ -115,6 +115,18 @@ void IREmitter::Discard() {
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Inst(Opcode::Discard);
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}
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void IREmitter::Barrier() {
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Inst(Opcode::Barrier);
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}
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void IREmitter::WorkgroupMemoryBarrier() {
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Inst(Opcode::WorkgroupMemoryBarrier);
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}
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void IREmitter::DeviceMemoryBarrier() {
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Inst(Opcode::DeviceMemoryBarrier);
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}
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U32 IREmitter::GetUserData(IR::ScalarReg reg) {
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return Inst<U32>(Opcode::GetUserData, reg);
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}
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@ -200,6 +212,10 @@ U1 IREmitter::GetVcc() {
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return Inst<U1>(Opcode::GetVcc);
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}
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U32 IREmitter::GetSccLo() {
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return Inst<U32>(Opcode::GetSccLo);
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}
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U32 IREmitter::GetVccLo() {
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return Inst<U32>(Opcode::GetVccLo);
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}
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@ -220,6 +236,10 @@ void IREmitter::SetVcc(const U1& value) {
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Inst(Opcode::SetVcc, value);
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}
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void IREmitter::SetSccLo(const U32& value) {
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Inst(Opcode::SetSccLo, value);
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}
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void IREmitter::SetVccLo(const U32& value) {
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Inst(Opcode::SetVccLo, value);
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}
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@ -240,22 +260,25 @@ void IREmitter::SetAttribute(IR::Attribute attribute, const F32& value, u32 comp
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Inst(Opcode::SetAttribute, attribute, value, Imm32(comp));
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}
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U32U64 IREmitter::ReadShared(int bit_size, bool is_signed, const U32& offset) {
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/*switch (bit_size) {
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Value IREmitter::LoadShared(int bit_size, bool is_signed, const U32& offset) {
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switch (bit_size) {
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case 8:
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return Inst<U32>(is_signed ? Opcode::ReadSharedS8 : Opcode::ReadSharedU8, offset);
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return Inst<U32>(is_signed ? Opcode::LoadSharedS8 : Opcode::LoadSharedU8, offset);
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case 16:
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return Inst<U32>(is_signed ? Opcode::ReadSharedS16 : Opcode::ReadSharedU16, offset);
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return Inst<U32>(is_signed ? Opcode::LoadSharedS16 : Opcode::LoadSharedU16, offset);
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case 32:
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return Inst<U32>(Opcode::ReadSharedU32, offset);
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return Inst<U32>(Opcode::LoadSharedU32, offset);
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case 64:
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return Inst<U64>(Opcode::ReadSharedU64, offset);
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return Inst<U64>(Opcode::LoadSharedU64, offset);
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case 128:
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return Inst(Opcode::LoadSharedU128, offset);
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default:
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UNREACHABLE_MSG("Invalid bit size {}", bit_size);
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}
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UNREACHABLE_MSG("Invalid bit size {}", bit_size);*/
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}
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void IREmitter::WriteShared(int bit_size, const Value& value, const U32& offset) {
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/*switch (bit_size) {
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switch (bit_size) {
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case 8:
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Inst(Opcode::WriteSharedU8, offset, value);
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break;
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@ -268,9 +291,12 @@ void IREmitter::WriteShared(int bit_size, const Value& value, const U32& offset)
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case 64:
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Inst(Opcode::WriteSharedU64, offset, value);
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break;
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case 128:
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Inst(Opcode::WriteSharedU128, offset, value);
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break;
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default:
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UNREACHABLE_MSG("Invalid bit size {}", bit_size);
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}*/
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}
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}
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U32 IREmitter::ReadConst(const Value& base, const U32& offset) {
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@ -603,6 +629,10 @@ F32 IREmitter::FPExp2(const F32& value) {
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return Inst<F32>(Opcode::FPExp2, value);
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}
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F32 IREmitter::FPLdexp(const F32& value, const U32& exp) {
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return Inst<F32>(Opcode::FPLdexp, value, exp);
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}
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F32 IREmitter::FPLog2(const F32& value) {
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return Inst<F32>(Opcode::FPLog2, value);
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}
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@ -810,6 +840,17 @@ U1 IREmitter::FPIsNan(const F32F64& value) {
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}
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}
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U1 IREmitter::FPIsInf(const F32F64& value) {
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switch (value.Type()) {
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case Type::F32:
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return Inst<U1>(Opcode::FPIsInf32, value);
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case Type::F64:
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return Inst<U1>(Opcode::FPIsInf64, value);
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default:
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ThrowInvalidType(value.Type());
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}
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}
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U1 IREmitter::FPOrdered(const F32F64& lhs, const F32F64& rhs) {
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if (lhs.Type() != rhs.Type()) {
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UNREACHABLE_MSG("Mismatching types {} and {}", lhs.Type(), rhs.Type());
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@ -866,6 +907,18 @@ U32U64 IREmitter::IAdd(const U32U64& a, const U32U64& b) {
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}
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}
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Value IREmitter::IAddCary(const U32& a, const U32& b) {
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if (a.Type() != b.Type()) {
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UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type());
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}
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switch (a.Type()) {
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case Type::U32:
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return Inst<U32>(Opcode::IAddCary32, a, b);
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default:
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ThrowInvalidType(a.Type());
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}
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}
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U32U64 IREmitter::ISub(const U32U64& a, const U32U64& b) {
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if (a.Type() != b.Type()) {
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UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type());
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@ -1142,6 +1195,13 @@ F32F64 IREmitter::ConvertIToF(size_t dest_bitsize, size_t src_bitsize, bool is_s
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}
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U16U32U64 IREmitter::UConvert(size_t result_bitsize, const U16U32U64& value) {
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switch (result_bitsize) {
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case 16:
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switch (value.Type()) {
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case Type::U32:
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return Inst<U16>(Opcode::ConvertU16U32, value);
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}
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}
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throw NotImplementedException("Conversion from {} to {} bits", value.Type(), result_bitsize);
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}
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@ -1163,6 +1223,73 @@ F16F32F64 IREmitter::FPConvert(size_t result_bitsize, const F16F32F64& value) {
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throw NotImplementedException("Conversion from {} to {} bits", value.Type(), result_bitsize);
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}
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Value IREmitter::ImageAtomicIAdd(const Value& handle, const Value& coords, const Value& value,
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TextureInstInfo info) {
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return Inst(Opcode::ImageAtomicIAdd32, Flags{info}, handle, coords, value);
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}
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Value IREmitter::ImageAtomicSMin(const Value& handle, const Value& coords, const Value& value,
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TextureInstInfo info) {
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return Inst(Opcode::ImageAtomicSMin32, Flags{info}, handle, coords, value);
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}
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Value IREmitter::ImageAtomicUMin(const Value& handle, const Value& coords, const Value& value,
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TextureInstInfo info) {
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return Inst(Opcode::ImageAtomicUMin32, Flags{info}, handle, coords, value);
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}
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Value IREmitter::ImageAtomicIMin(const Value& handle, const Value& coords, const Value& value,
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bool is_signed, TextureInstInfo info) {
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return is_signed ? ImageAtomicSMin(handle, coords, value, info)
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: ImageAtomicUMin(handle, coords, value, info);
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}
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Value IREmitter::ImageAtomicSMax(const Value& handle, const Value& coords, const Value& value,
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TextureInstInfo info) {
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return Inst(Opcode::ImageAtomicSMax32, Flags{info}, handle, coords, value);
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}
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Value IREmitter::ImageAtomicUMax(const Value& handle, const Value& coords, const Value& value,
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TextureInstInfo info) {
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return Inst(Opcode::ImageAtomicUMax32, Flags{info}, handle, coords, value);
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}
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Value IREmitter::ImageAtomicIMax(const Value& handle, const Value& coords, const Value& value,
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bool is_signed, TextureInstInfo info) {
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return is_signed ? ImageAtomicSMax(handle, coords, value, info)
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: ImageAtomicUMax(handle, coords, value, info);
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}
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Value IREmitter::ImageAtomicInc(const Value& handle, const Value& coords, const Value& value,
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TextureInstInfo info) {
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return Inst(Opcode::ImageAtomicInc32, Flags{info}, handle, coords, value);
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}
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Value IREmitter::ImageAtomicDec(const Value& handle, const Value& coords, const Value& value,
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TextureInstInfo info) {
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return Inst(Opcode::ImageAtomicDec32, Flags{info}, handle, coords, value);
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}
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Value IREmitter::ImageAtomicAnd(const Value& handle, const Value& coords, const Value& value,
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TextureInstInfo info) {
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return Inst(Opcode::ImageAtomicAnd32, Flags{info}, handle, coords, value);
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}
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Value IREmitter::ImageAtomicOr(const Value& handle, const Value& coords, const Value& value,
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TextureInstInfo info) {
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return Inst(Opcode::ImageAtomicOr32, Flags{info}, handle, coords, value);
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}
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Value IREmitter::ImageAtomicXor(const Value& handle, const Value& coords, const Value& value,
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TextureInstInfo info) {
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return Inst(Opcode::ImageAtomicXor32, Flags{info}, handle, coords, value);
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}
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Value IREmitter::ImageAtomicExchange(const Value& handle, const Value& coords, const Value& value,
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TextureInstInfo info) {
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return Inst(Opcode::ImageAtomicExchange32, Flags{info}, handle, coords, value);
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}
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Value IREmitter::ImageSampleImplicitLod(const Value& handle, const Value& coords, const F32& bias,
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const Value& offset, const F32& lod_clamp,
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TextureInstInfo info) {
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