mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-18 01:14:56 +00:00
video_core: Preliminary storage image support and more (#188)
* vk_rasterizer: Clear depth buffer when DB_RENDER_CONTROL says so * video_core: Preliminary storage image support, more opcodes * renderer_vulkan: a fix for vertex buffers merging * renderer_vulkan: a heuristic for blend override when alpha out is masked --------- Co-authored-by: psucien <bad_cast@protonmail.com>
This commit is contained in:
parent
23f11a3fda
commit
7b1a317b09
30 changed files with 429 additions and 101 deletions
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@ -306,6 +306,15 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::IMAGE_SAMPLE:
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translator.IMAGE_SAMPLE(inst);
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break;
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case Opcode::IMAGE_STORE:
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translator.IMAGE_STORE(inst);
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break;
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case Opcode::IMAGE_LOAD_MIP:
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translator.IMAGE_LOAD_MIP(inst);
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break;
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case Opcode::V_CMP_GE_I32:
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translator.V_CMP_U32(ConditionOp::GE, true, false, inst);
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break;
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case Opcode::V_CMP_EQ_I32:
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translator.V_CMP_U32(ConditionOp::EQ, true, false, inst);
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break;
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@ -331,28 +340,31 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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translator.V_CMP_U32(ConditionOp::TRU, false, false, inst);
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break;
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case Opcode::V_CMP_NEQ_F32:
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translator.V_CMP_F32(ConditionOp::LG, inst);
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translator.V_CMP_F32(ConditionOp::LG, false, inst);
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break;
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case Opcode::V_CMP_F_F32:
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translator.V_CMP_F32(ConditionOp::F, inst);
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translator.V_CMP_F32(ConditionOp::F, false, inst);
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break;
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case Opcode::V_CMP_LT_F32:
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translator.V_CMP_F32(ConditionOp::LT, inst);
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translator.V_CMP_F32(ConditionOp::LT, false, inst);
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break;
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case Opcode::V_CMP_EQ_F32:
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translator.V_CMP_F32(ConditionOp::EQ, inst);
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translator.V_CMP_F32(ConditionOp::EQ, false, inst);
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break;
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case Opcode::V_CMP_LE_F32:
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translator.V_CMP_F32(ConditionOp::LE, inst);
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translator.V_CMP_F32(ConditionOp::LE, false, inst);
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break;
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case Opcode::V_CMP_GT_F32:
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translator.V_CMP_F32(ConditionOp::GT, inst);
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translator.V_CMP_F32(ConditionOp::GT, false, inst);
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break;
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case Opcode::V_CMP_LG_F32:
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translator.V_CMP_F32(ConditionOp::LG, inst);
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translator.V_CMP_F32(ConditionOp::LG, false, inst);
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break;
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case Opcode::V_CMP_GE_F32:
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translator.V_CMP_F32(ConditionOp::GE, inst);
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translator.V_CMP_F32(ConditionOp::GE, false, inst);
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break;
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case Opcode::V_CMP_NLE_F32:
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translator.V_CMP_F32(ConditionOp::GT, false, inst);
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break;
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case Opcode::S_CMP_LG_U32:
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translator.S_CMP(ConditionOp::LG, false, inst);
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@ -378,6 +390,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_CNDMASK_B32:
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translator.V_CNDMASK_B32(inst);
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break;
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case Opcode::TBUFFER_LOAD_FORMAT_XYZ:
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translator.BUFFER_LOAD_FORMAT(3, true, inst);
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break;
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case Opcode::TBUFFER_LOAD_FORMAT_XYZW:
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translator.BUFFER_LOAD_FORMAT(4, true, inst);
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break;
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@ -414,6 +429,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_MIN_F32:
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translator.V_MIN_F32(inst);
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break;
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case Opcode::V_MIN_I32:
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translator.V_MIN_I32(inst);
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break;
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case Opcode::V_MIN3_F32:
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translator.V_MIN3_F32(inst);
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break;
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@ -435,6 +453,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_CVT_U32_F32:
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translator.V_CVT_U32_F32(inst);
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break;
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case Opcode::V_CVT_I32_F32:
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translator.V_CVT_I32_F32(inst);
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break;
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case Opcode::V_SUBREV_F32:
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translator.V_SUBREV_F32(inst);
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break;
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@ -447,12 +468,61 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_SUBREV_I32:
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translator.V_SUBREV_I32(inst);
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break;
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case Opcode::V_CMPX_F_F32:
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translator.V_CMP_F32(ConditionOp::F, true, inst);
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break;
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case Opcode::V_CMPX_LT_F32:
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translator.V_CMP_F32(ConditionOp::LT, true, inst);
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break;
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case Opcode::V_CMPX_EQ_F32:
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translator.V_CMP_F32(ConditionOp::EQ, true, inst);
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break;
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case Opcode::V_CMPX_LE_F32:
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translator.V_CMP_F32(ConditionOp::LE, true, inst);
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break;
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case Opcode::V_CMPX_GT_F32:
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translator.V_CMP_F32(ConditionOp::GT, true, inst);
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break;
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case Opcode::V_CMPX_LG_F32:
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translator.V_CMP_F32(ConditionOp::LG, true, inst);
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break;
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case Opcode::V_CMPX_GE_F32:
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translator.V_CMP_F32(ConditionOp::GE, true, inst);
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break;
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case Opcode::V_CMPX_NGE_F32:
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translator.V_CMP_F32(ConditionOp::LT, true, inst);
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break;
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case Opcode::V_CMPX_NLG_F32:
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translator.V_CMP_F32(ConditionOp::EQ, true, inst);
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break;
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case Opcode::V_CMPX_NGT_F32:
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translator.V_CMP_F32(ConditionOp::LE, true, inst);
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break;
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case Opcode::V_CMPX_NLE_F32:
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translator.V_CMP_F32(ConditionOp::GT, true, inst);
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break;
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case Opcode::V_CMPX_NEQ_F32:
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translator.V_CMP_F32(ConditionOp::LG, true, inst);
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break;
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case Opcode::V_CMPX_NLT_F32:
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translator.V_CMP_F32(ConditionOp::GE, true, inst);
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break;
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case Opcode::V_CMPX_TRU_F32:
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translator.V_CMP_F32(ConditionOp::TRU, true, inst);
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break;
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case Opcode::V_CMP_LE_U32:
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translator.V_CMP_U32(ConditionOp::LE, false, false, inst);
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break;
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case Opcode::V_CMP_GT_I32:
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translator.V_CMP_U32(ConditionOp::GT, true, false, inst);
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break;
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case Opcode::V_CMP_LT_I32:
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translator.V_CMP_U32(ConditionOp::LT, true, false, inst);
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break;
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case Opcode::V_CMPX_LT_I32:
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translator.V_CMP_U32(ConditionOp::LT, true, true, inst);
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break;
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case Opcode::V_CMPX_F_U32:
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translator.V_CMP_U32(ConditionOp::F, false, true, inst);
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break;
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@ -540,6 +610,18 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_BCNT_U32_B32:
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translator.V_BCNT_U32_B32(inst);
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break;
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case Opcode::V_MAX3_F32:
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translator.V_MAX3_F32(inst);
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break;
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case Opcode::DS_SWIZZLE_B32:
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translator.DS_SWIZZLE_B32(inst);
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break;
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case Opcode::V_MUL_LO_U32:
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translator.V_MUL_LO_U32(inst);
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break;
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case Opcode::S_BFM_B32:
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translator.S_BFM_B32(inst);
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break;
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case Opcode::S_NOP:
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case Opcode::S_CBRANCH_EXECZ:
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case Opcode::S_CBRANCH_SCC0:
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