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https://github.com/shadps4-emu/shadPS4.git
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video: Import new shader recompiler + display a triangle (#142)
This commit is contained in:
parent
8cf64a33b2
commit
8730968385
103 changed files with 17793 additions and 729 deletions
209
src/shader_recompiler/frontend/control_flow_graph.cpp
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209
src/shader_recompiler/frontend/control_flow_graph.cpp
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@ -0,0 +1,209 @@
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <algorithm>
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#include "common/assert.h"
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#include "shader_recompiler/frontend/control_flow_graph.h"
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namespace Shader::Gcn {
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struct Compare {
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bool operator()(const Block& lhs, u32 rhs) const noexcept {
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return lhs.begin < rhs;
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}
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bool operator()(u32 lhs, const Block& rhs) const noexcept {
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return lhs < rhs.begin;
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}
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bool operator()(const Block& lhs, const Block& rhs) const noexcept {
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return lhs.begin < rhs.begin;
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}
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};
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static IR::Condition MakeCondition(Opcode opcode) {
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switch (opcode) {
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case Opcode::S_CBRANCH_SCC0:
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return IR::Condition::Scc0;
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case Opcode::S_CBRANCH_SCC1:
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return IR::Condition::Scc1;
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case Opcode::S_CBRANCH_VCCZ:
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return IR::Condition::Vccz;
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case Opcode::S_CBRANCH_VCCNZ:
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return IR::Condition::Vccnz;
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case Opcode::S_CBRANCH_EXECZ:
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return IR::Condition::Execz;
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case Opcode::S_CBRANCH_EXECNZ:
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return IR::Condition::Execnz;
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default:
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return IR::Condition::True;
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}
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}
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CFG::CFG(ObjectPool<Block>& block_pool_, std::span<const GcnInst> inst_list_)
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: block_pool{block_pool_}, inst_list{inst_list_} {
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index_to_pc.resize(inst_list.size());
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EmitLabels();
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EmitBlocks();
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LinkBlocks();
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}
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void CFG::EmitLabels() {
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// Always set a label at entry point.
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u32 pc = 0;
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labels.push_back(pc);
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const auto add_label = [this](u32 address) {
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const auto it = std::ranges::find(labels, address);
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if (it == labels.end()) {
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labels.push_back(address);
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}
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};
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// Iterate instruction list and add labels to branch targets.
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for (u32 i = 0; i < inst_list.size(); i++) {
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index_to_pc[i] = pc;
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const GcnInst inst = inst_list[i];
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if (inst.IsUnconditionalBranch()) {
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const u32 target = inst.BranchTarget(pc);
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add_label(target);
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} else if (inst.IsConditionalBranch()) {
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const u32 true_label = inst.BranchTarget(pc);
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const u32 false_label = pc + inst.length;
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add_label(true_label);
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add_label(false_label);
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} else if (inst.opcode == Opcode::S_ENDPGM) {
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const u32 next_label = pc + inst.length;
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add_label(next_label);
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}
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pc += inst.length;
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}
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// Sort labels to make sure block insertion is correct.
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std::ranges::sort(labels);
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}
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void CFG::EmitBlocks() {
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const auto get_index = [this](Label label) -> size_t {
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if (label == 0) {
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return 0ULL;
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}
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const auto it_index = std::ranges::lower_bound(index_to_pc, label);
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ASSERT(it_index != index_to_pc.end() || label > index_to_pc.back());
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return std::distance(index_to_pc.begin(), std::prev(it_index));
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};
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for (auto it = labels.begin(); it != labels.end(); it++) {
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const Label start = *it;
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const auto next_it = std::next(it);
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const bool is_last = next_it == labels.end();
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if (is_last) {
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// Last label is special.
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return;
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}
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const Label end = *next_it;
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const size_t end_index = get_index(end);
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const auto& end_inst = inst_list[end_index];
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// Insert block between the labels using the last instruction
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// as an indicator for branching type.
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Block* block = block_pool.Create();
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block->begin = start;
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block->end = end;
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block->begin_index = get_index(start);
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block->end_index = end_index;
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block->end_inst = end_inst;
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block->cond = MakeCondition(end_inst.opcode);
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blocks.insert(*block);
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}
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}
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void CFG::LinkBlocks() {
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const auto get_block = [this](u32 address) {
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const auto it = blocks.find(address, Compare{});
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ASSERT_MSG(it != blocks.end() && it->begin == address);
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return &*it;
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};
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for (auto& block : blocks) {
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const auto end_inst{block.end_inst};
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// If the block doesn't end with a branch we simply
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// need to link with the next block.
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if (!end_inst.IsTerminateInstruction()) {
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block.branch_true = get_block(block.end);
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block.end_class = EndClass::Branch;
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continue;
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}
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// Find the branch targets from the instruction and link the blocks.
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// Note: Block end address is one instruction after end_inst.
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const u32 branch_pc = block.end - end_inst.length;
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const u32 target_pc = end_inst.BranchTarget(branch_pc);
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if (end_inst.IsUnconditionalBranch()) {
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block.branch_true = get_block(target_pc);
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block.end_class = EndClass::Branch;
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} else if (end_inst.IsConditionalBranch()) {
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block.branch_true = get_block(target_pc);
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block.branch_false = get_block(block.end);
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block.end_class = EndClass::Branch;
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} else {
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// Exit blocks don't link to anything.
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block.end_class = EndClass::Exit;
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}
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}
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}
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std::string CFG::Dot() const {
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int node_uid{0};
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const auto name_of = [](const Block& block) { return fmt::format("\"{:#x}\"", block.begin); };
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std::string dot{"digraph shader {\n"};
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dot += fmt::format("\tsubgraph cluster_{} {{\n", 0);
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dot += fmt::format("\t\tnode [style=filled];\n");
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for (const Block& block : blocks) {
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const std::string name{name_of(block)};
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const auto add_branch = [&](Block* branch, bool add_label) {
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dot += fmt::format("\t\t{}->{}", name, name_of(*branch));
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if (add_label && block.cond != IR::Condition::True &&
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block.cond != IR::Condition::False) {
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dot += fmt::format(" [label=\"{}\"]", block.cond);
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}
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dot += '\n';
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};
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dot += fmt::format("\t\t{};\n", name);
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switch (block.end_class) {
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case EndClass::Branch:
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if (block.cond != IR::Condition::False) {
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add_branch(block.branch_true, true);
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}
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if (block.cond != IR::Condition::True) {
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add_branch(block.branch_false, false);
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}
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break;
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case EndClass::Exit:
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dot += fmt::format("\t\t{}->N{};\n", name, node_uid);
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dot +=
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fmt::format("\t\tN{} [label=\"Exit\"][shape=square][style=stripped];\n", node_uid);
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++node_uid;
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break;
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// case EndClass::Kill:
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// dot += fmt::format("\t\t{}->N{};\n", name, node_uid);
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// dot += fmt::format("\t\tN{} [label=\"Kill\"][shape=square][style=stripped];\n",
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// node_uid);
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// ++node_uid;
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// break;
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}
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}
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dot += "\t\tlabel = \"main\";\n\t}\n";
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if (blocks.empty()) {
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dot += "Start;\n";
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} else {
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dot += fmt::format("\tStart -> {};\n", name_of(*blocks.begin()));
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}
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dot += fmt::format("\tStart [shape=diamond];\n");
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dot += "}\n";
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return dot;
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}
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} // namespace Shader::Gcn
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66
src/shader_recompiler/frontend/control_flow_graph.h
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66
src/shader_recompiler/frontend/control_flow_graph.h
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <span>
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#include <string>
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#include <boost/container/small_vector.hpp>
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#include <boost/intrusive/set.hpp>
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#include "common/types.h"
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#include "shader_recompiler/frontend/instruction.h"
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#include "shader_recompiler/ir/condition.h"
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#include "shader_recompiler/object_pool.h"
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namespace Shader::Gcn {
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using Hook =
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boost::intrusive::set_base_hook<boost::intrusive::link_mode<boost::intrusive::normal_link>>;
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enum class EndClass {
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Branch, ///< Block ends with a (un)conditional branch.
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Exit, ///< Block ends with an exit instruction.
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};
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/// A block represents a linear range of instructions.
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struct Block : Hook {
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[[nodiscard]] bool Contains(u32 pc) const noexcept;
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bool operator<(const Block& rhs) const noexcept {
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return begin < rhs.begin;
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}
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u32 begin;
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u32 end;
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u32 begin_index;
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u32 end_index;
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IR::Condition cond{};
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GcnInst end_inst{};
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EndClass end_class{};
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Block* branch_true{};
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Block* branch_false{};
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};
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class CFG {
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using Label = u32;
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public:
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explicit CFG(ObjectPool<Block>& block_pool, std::span<const GcnInst> inst_list);
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[[nodiscard]] std::string Dot() const;
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private:
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void EmitLabels();
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void EmitBlocks();
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void LinkBlocks();
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public:
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ObjectPool<Block>& block_pool;
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std::span<const GcnInst> inst_list;
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std::vector<u32> index_to_pc;
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boost::container::small_vector<Label, 16> labels;
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boost::intrusive::set<Block> blocks;
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};
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} // namespace Shader::Gcn
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1097
src/shader_recompiler/frontend/decode.cpp
Normal file
1097
src/shader_recompiler/frontend/decode.cpp
Normal file
File diff suppressed because it is too large
Load diff
97
src/shader_recompiler/frontend/decode.h
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97
src/shader_recompiler/frontend/decode.h
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include "shader_recompiler/frontend/instruction.h"
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namespace Shader::Gcn {
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struct InstFormat {
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InstClass inst_class = InstClass::Undefined;
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InstCategory inst_category = InstCategory::Undefined;
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u32 src_count = 0;
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u32 dst_count = 0;
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ScalarType src_type = ScalarType::Undefined;
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ScalarType dst_type = ScalarType::Undefined;
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};
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InstEncoding GetInstructionEncoding(u32 token);
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u32 GetEncodingLength(InstEncoding encoding);
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InstFormat InstructionFormat(InstEncoding encoding, u32 opcode);
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Opcode DecodeOpcode(u32 token);
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class GcnCodeSlice {
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public:
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GcnCodeSlice(const u32* ptr, const u32* end) : m_ptr(ptr), m_end(end) {}
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GcnCodeSlice(const GcnCodeSlice& other) = default;
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~GcnCodeSlice() = default;
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u32 at(u32 id) const {
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return m_ptr[id];
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}
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u32 readu32() {
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return *(m_ptr++);
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}
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u64 readu64() {
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const u64 value = *(u64*)m_ptr;
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m_ptr += 2;
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return value;
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}
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bool atEnd() const {
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return m_ptr == m_end;
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}
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private:
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const u32* m_ptr{};
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const u32* m_end{};
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};
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class GcnDecodeContext {
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public:
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GcnInst decodeInstruction(GcnCodeSlice& code);
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private:
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uint32_t getEncodingLength(InstEncoding encoding);
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uint32_t getOpMapOffset(InstEncoding encoding);
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uint32_t mapEncodingOp(InstEncoding encoding, Opcode opcode);
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void updateInstructionMeta(InstEncoding encoding);
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uint32_t getMimgModifier(Opcode opcode);
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void repairOperandType();
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OperandField getOperandField(uint32_t code);
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void decodeInstruction32(InstEncoding encoding, GcnCodeSlice& code);
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void decodeInstruction64(InstEncoding encoding, GcnCodeSlice& code);
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void decodeLiteralConstant(InstEncoding encoding, GcnCodeSlice& code);
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// 32 bits encodings
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void decodeInstructionSOP1(uint32_t hexInstruction);
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void decodeInstructionSOPP(uint32_t hexInstruction);
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void decodeInstructionSOPC(uint32_t hexInstruction);
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void decodeInstructionSOPK(uint32_t hexInstruction);
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void decodeInstructionSOP2(uint32_t hexInstruction);
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void decodeInstructionVOP1(uint32_t hexInstruction);
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void decodeInstructionVOPC(uint32_t hexInstruction);
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void decodeInstructionVOP2(uint32_t hexInstruction);
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void decodeInstructionSMRD(uint32_t hexInstruction);
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void decodeInstructionVINTRP(uint32_t hexInstruction);
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// 64 bits encodings
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void decodeInstructionVOP3(uint64_t hexInstruction);
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void decodeInstructionMUBUF(uint64_t hexInstruction);
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void decodeInstructionMTBUF(uint64_t hexInstruction);
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void decodeInstructionMIMG(uint64_t hexInstruction);
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void decodeInstructionDS(uint64_t hexInstruction);
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void decodeInstructionEXP(uint64_t hexInstruction);
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private:
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GcnInst m_instruction;
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};
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} // namespace Shader::Gcn
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3733
src/shader_recompiler/frontend/format.cpp
Normal file
3733
src/shader_recompiler/frontend/format.cpp
Normal file
File diff suppressed because it is too large
Load diff
50
src/shader_recompiler/frontend/instruction.cpp
Normal file
50
src/shader_recompiler/frontend/instruction.cpp
Normal file
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/assert.h"
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#include "shader_recompiler/frontend/instruction.h"
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namespace Shader::Gcn {
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u32 GcnInst::BranchTarget(u32 pc) const {
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const s16 simm = static_cast<s16>(control.sopp.simm * 4);
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const u32 target = pc + simm + 4;
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return target;
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}
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bool GcnInst::IsTerminateInstruction() const {
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return IsUnconditionalBranch() || IsConditionalBranch() || IsFork() ||
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opcode == Opcode::S_ENDPGM;
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}
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bool GcnInst::IsUnconditionalBranch() const {
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return opcode == Opcode::S_BRANCH;
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}
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bool GcnInst::IsFork() const {
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return opcode == Opcode::S_CBRANCH_I_FORK || opcode == Opcode::S_CBRANCH_G_FORK ||
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opcode == Opcode::S_CBRANCH_JOIN;
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}
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bool GcnInst::IsConditionalBranch() const {
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switch (opcode) {
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case Opcode::S_CBRANCH_SCC0:
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case Opcode::S_CBRANCH_SCC1:
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case Opcode::S_CBRANCH_VCCZ:
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case Opcode::S_CBRANCH_VCCNZ:
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case Opcode::S_CBRANCH_EXECZ:
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case Opcode::S_CBRANCH_EXECNZ:
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return true;
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case Opcode::S_CBRANCH_CDBGSYS:
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case Opcode::S_CBRANCH_CDBGUSER:
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case Opcode::S_CBRANCH_CDBGSYS_OR_USER:
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case Opcode::S_CBRANCH_CDBGSYS_AND_USER:
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UNIMPLEMENTED();
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return true;
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default:
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break;
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}
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return false;
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}
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} // namespace Shader::Gcn
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208
src/shader_recompiler/frontend/instruction.h
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208
src/shader_recompiler/frontend/instruction.h
Normal file
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <limits>
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#include "common/bit_field.h"
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#include "shader_recompiler/frontend/opcodes.h"
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namespace Shader::Gcn {
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constexpr u32 GcnMaxSrcCount = 4;
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constexpr u32 GcnMaxDstCount = 2;
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enum OperandFieldRange {
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ScalarGPRMin = 0,
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ScalarGPRMax = 103,
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SignedConstIntPosMin = 129,
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SignedConstIntPosMax = 192,
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SignedConstIntNegMin = 193,
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SignedConstIntNegMax = 208,
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ConstFloatMin = 240,
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VectorGPRMin = 256,
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VectorGPRMax = 511
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};
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|
||||
/// These are applied after loading an operand register.
|
||||
struct InputModifiers {
|
||||
bool neg = false;
|
||||
bool abs = false;
|
||||
};
|
||||
|
||||
/// These are applied before storing an operand register.
|
||||
struct OutputModifiers {
|
||||
bool clamp = false;
|
||||
float multiplier = std::numeric_limits<float>::quiet_NaN();
|
||||
};
|
||||
|
||||
struct InstOperand {
|
||||
OperandField field = OperandField::Undefined;
|
||||
ScalarType type = ScalarType::Undefined;
|
||||
InputModifiers input_modifier = {};
|
||||
OutputModifiers output_modifier = {};
|
||||
u32 code = 0xFFFFFFFF;
|
||||
};
|
||||
|
||||
struct Operand {
|
||||
OperandField field = OperandField::Undefined;
|
||||
ScalarType type = ScalarType::Undefined;
|
||||
union {
|
||||
InputModifiers input_modifier = {};
|
||||
OutputModifiers output_modifier;
|
||||
};
|
||||
u32 code = 0xFFFFFFFF;
|
||||
};
|
||||
|
||||
struct InstSOPK {
|
||||
u16 simm;
|
||||
};
|
||||
|
||||
struct InstSOPP {
|
||||
u16 simm;
|
||||
};
|
||||
|
||||
struct InstVOP3 {
|
||||
Operand vdst;
|
||||
Operand src0;
|
||||
Operand src1;
|
||||
Operand src2;
|
||||
};
|
||||
|
||||
struct SMRD {
|
||||
u8 offset;
|
||||
bool imm;
|
||||
u8 sbase;
|
||||
};
|
||||
|
||||
struct InstControlSOPK {
|
||||
BitField<0, 16, u32> simm;
|
||||
};
|
||||
|
||||
struct InstControlSOPP {
|
||||
BitField<0, 16, u32> simm;
|
||||
};
|
||||
|
||||
struct InstControlVOP3 {
|
||||
u64 : 8;
|
||||
u64 abs : 3;
|
||||
u64 clmp : 1;
|
||||
u64 : 47;
|
||||
u64 omod : 2;
|
||||
u64 neg : 3;
|
||||
};
|
||||
|
||||
struct InstControlSMRD {
|
||||
u32 offset : 8;
|
||||
u32 imm : 1;
|
||||
u32 count : 5;
|
||||
u32 : 18;
|
||||
};
|
||||
|
||||
struct InstControlMUBUF {
|
||||
u64 offset : 12;
|
||||
u64 offen : 1;
|
||||
u64 idxen : 1;
|
||||
u64 glc : 1;
|
||||
u64 : 1;
|
||||
u64 lds : 1;
|
||||
u64 : 37;
|
||||
u64 slc : 1;
|
||||
u64 tfe : 1;
|
||||
u64 count : 3;
|
||||
u64 size : 5;
|
||||
};
|
||||
|
||||
struct InstControlMTBUF {
|
||||
u64 offset : 12;
|
||||
u64 offen : 1;
|
||||
u64 idxen : 1;
|
||||
u64 glc : 1;
|
||||
u64 : 4;
|
||||
u64 dfmt : 4;
|
||||
u64 nfmt : 3;
|
||||
u64 : 28;
|
||||
u64 slc : 1;
|
||||
u64 tfe : 1;
|
||||
u64 count : 3;
|
||||
u64 size : 5;
|
||||
};
|
||||
|
||||
struct InstControlMIMG {
|
||||
u64 : 8;
|
||||
u64 dmask : 4;
|
||||
u64 unrm : 1;
|
||||
u64 glc : 1;
|
||||
u64 da : 1;
|
||||
u64 r128 : 1;
|
||||
u64 tfe : 1;
|
||||
u64 lwe : 1;
|
||||
u64 : 7;
|
||||
u64 slc : 1;
|
||||
u64 mod : 32;
|
||||
u64 : 6;
|
||||
};
|
||||
|
||||
struct InstControlDS {
|
||||
u64 offset0 : 8;
|
||||
u64 offset1 : 8;
|
||||
u64 : 1;
|
||||
u64 gds : 1;
|
||||
u64 dual : 1;
|
||||
u64 sign : 1;
|
||||
u64 relative : 1;
|
||||
u64 stride : 1;
|
||||
u64 size : 4;
|
||||
u64 : 38;
|
||||
};
|
||||
|
||||
struct InstControlVINTRP {
|
||||
u32 : 8;
|
||||
u32 chan : 2;
|
||||
u32 attr : 6;
|
||||
u32 : 16;
|
||||
};
|
||||
|
||||
struct InstControlEXP {
|
||||
u64 en : 4;
|
||||
u64 target : 6;
|
||||
u64 compr : 1;
|
||||
u64 done : 1;
|
||||
u64 vm : 1;
|
||||
u64 reserved : 51;
|
||||
};
|
||||
|
||||
union InstControl {
|
||||
InstControlSOPK sopk;
|
||||
InstControlSOPP sopp;
|
||||
InstControlVOP3 vop3;
|
||||
InstControlSMRD smrd;
|
||||
InstControlMUBUF mubuf;
|
||||
InstControlMTBUF mtbuf;
|
||||
InstControlMIMG mimg;
|
||||
InstControlDS ds;
|
||||
InstControlVINTRP vintrp;
|
||||
InstControlEXP exp;
|
||||
};
|
||||
|
||||
struct GcnInst {
|
||||
Opcode opcode;
|
||||
InstEncoding encoding;
|
||||
InstClass inst_class;
|
||||
InstCategory category;
|
||||
InstControl control;
|
||||
u32 length;
|
||||
u32 src_count;
|
||||
u32 dst_count;
|
||||
std::array<InstOperand, GcnMaxSrcCount> src;
|
||||
std::array<InstOperand, GcnMaxDstCount> dst;
|
||||
|
||||
u32 BranchTarget(u32 pc) const;
|
||||
|
||||
bool IsTerminateInstruction() const;
|
||||
bool IsUnconditionalBranch() const;
|
||||
bool IsConditionalBranch() const;
|
||||
bool IsFork() const;
|
||||
};
|
||||
|
||||
} // namespace Shader::Gcn
|
10
src/shader_recompiler/frontend/module.h
Normal file
10
src/shader_recompiler/frontend/module.h
Normal file
|
@ -0,0 +1,10 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
void Translate();
|
||||
|
||||
} // namespace Shader::Gcn
|
2494
src/shader_recompiler/frontend/opcodes.h
Normal file
2494
src/shader_recompiler/frontend/opcodes.h
Normal file
File diff suppressed because it is too large
Load diff
829
src/shader_recompiler/frontend/structured_control_flow.cpp
Normal file
829
src/shader_recompiler/frontend/structured_control_flow.cpp
Normal file
|
@ -0,0 +1,829 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include <algorithm>
|
||||
#include <memory>
|
||||
#include <string>
|
||||
#include <unordered_map>
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
#include <boost/intrusive/list.hpp>
|
||||
#include <fmt/format.h>
|
||||
#include "shader_recompiler/frontend/structured_control_flow.h"
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
#include "shader_recompiler/ir/ir_emitter.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
namespace {
|
||||
|
||||
struct Statement;
|
||||
|
||||
// Use normal_link because we are not guaranteed to destroy the tree in order
|
||||
using ListBaseHook =
|
||||
boost::intrusive::list_base_hook<boost::intrusive::link_mode<boost::intrusive::normal_link>>;
|
||||
|
||||
using Tree = boost::intrusive::list<Statement,
|
||||
// Allow using Statement without a definition
|
||||
boost::intrusive::base_hook<ListBaseHook>,
|
||||
// Avoid linear complexity on splice, size is never called
|
||||
boost::intrusive::constant_time_size<false>>;
|
||||
using Node = Tree::iterator;
|
||||
|
||||
enum class StatementType {
|
||||
Code,
|
||||
Goto,
|
||||
Label,
|
||||
If,
|
||||
Loop,
|
||||
Break,
|
||||
Return,
|
||||
Kill,
|
||||
Unreachable,
|
||||
Function,
|
||||
Identity,
|
||||
Not,
|
||||
Or,
|
||||
SetVariable,
|
||||
Variable,
|
||||
};
|
||||
|
||||
bool HasChildren(StatementType type) {
|
||||
switch (type) {
|
||||
case StatementType::If:
|
||||
case StatementType::Loop:
|
||||
case StatementType::Function:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
struct Goto {};
|
||||
struct Label {};
|
||||
struct If {};
|
||||
struct Loop {};
|
||||
struct Break {};
|
||||
struct Return {};
|
||||
struct Kill {};
|
||||
struct Unreachable {};
|
||||
struct FunctionTag {};
|
||||
struct Identity {};
|
||||
struct Not {};
|
||||
struct Or {};
|
||||
struct SetVariable {};
|
||||
struct Variable {};
|
||||
|
||||
struct Statement : ListBaseHook {
|
||||
Statement(const Block* block_, Statement* up_)
|
||||
: block{block_}, up{up_}, type{StatementType::Code} {}
|
||||
Statement(Goto, Statement* cond_, Node label_, Statement* up_)
|
||||
: label{label_}, cond{cond_}, up{up_}, type{StatementType::Goto} {}
|
||||
Statement(Label, u32 id_, Statement* up_) : id{id_}, up{up_}, type{StatementType::Label} {}
|
||||
Statement(If, Statement* cond_, Tree&& children_, Statement* up_)
|
||||
: children{std::move(children_)}, cond{cond_}, up{up_}, type{StatementType::If} {}
|
||||
Statement(Loop, Statement* cond_, Tree&& children_, Statement* up_)
|
||||
: children{std::move(children_)}, cond{cond_}, up{up_}, type{StatementType::Loop} {}
|
||||
Statement(Break, Statement* cond_, Statement* up_)
|
||||
: cond{cond_}, up{up_}, type{StatementType::Break} {}
|
||||
Statement(Return, Statement* up_) : up{up_}, type{StatementType::Return} {}
|
||||
Statement(Kill, Statement* up_) : up{up_}, type{StatementType::Kill} {}
|
||||
Statement(Unreachable, Statement* up_) : up{up_}, type{StatementType::Unreachable} {}
|
||||
Statement(FunctionTag) : children{}, type{StatementType::Function} {}
|
||||
Statement(Identity, IR::Condition cond_, Statement* up_)
|
||||
: guest_cond{cond_}, up{up_}, type{StatementType::Identity} {}
|
||||
Statement(Not, Statement* op_, Statement* up_) : op{op_}, up{up_}, type{StatementType::Not} {}
|
||||
Statement(Or, Statement* op_a_, Statement* op_b_, Statement* up_)
|
||||
: op_a{op_a_}, op_b{op_b_}, up{up_}, type{StatementType::Or} {}
|
||||
Statement(SetVariable, u32 id_, Statement* op_, Statement* up_)
|
||||
: op{op_}, id{id_}, up{up_}, type{StatementType::SetVariable} {}
|
||||
Statement(Variable, u32 id_, Statement* up_)
|
||||
: id{id_}, up{up_}, type{StatementType::Variable} {}
|
||||
|
||||
~Statement() {
|
||||
if (HasChildren(type)) {
|
||||
std::destroy_at(&children);
|
||||
}
|
||||
}
|
||||
|
||||
union {
|
||||
const Block* block;
|
||||
Node label;
|
||||
Tree children;
|
||||
IR::Condition guest_cond;
|
||||
Statement* op;
|
||||
Statement* op_a;
|
||||
u32 location;
|
||||
s32 branch_offset;
|
||||
};
|
||||
union {
|
||||
Statement* cond;
|
||||
Statement* op_b;
|
||||
u32 id;
|
||||
};
|
||||
Statement* up{};
|
||||
StatementType type;
|
||||
};
|
||||
|
||||
std::string DumpExpr(const Statement* stmt) {
|
||||
switch (stmt->type) {
|
||||
case StatementType::Identity:
|
||||
return fmt::format("{}", stmt->guest_cond);
|
||||
case StatementType::Not:
|
||||
return fmt::format("!{}", DumpExpr(stmt->op));
|
||||
case StatementType::Or:
|
||||
return fmt::format("{} || {}", DumpExpr(stmt->op_a), DumpExpr(stmt->op_b));
|
||||
case StatementType::Variable:
|
||||
return fmt::format("goto_L{}", stmt->id);
|
||||
default:
|
||||
return "<invalid type>";
|
||||
}
|
||||
}
|
||||
|
||||
[[maybe_unused]] std::string DumpTree(const Tree& tree, u32 indentation = 0) {
|
||||
std::string ret;
|
||||
std::string indent(indentation, ' ');
|
||||
for (auto stmt = tree.begin(); stmt != tree.end(); ++stmt) {
|
||||
switch (stmt->type) {
|
||||
case StatementType::Code:
|
||||
ret += fmt::format("{} Block {:04x} -> {:04x} (0x{:016x});\n", indent,
|
||||
stmt->block->begin, stmt->block->end,
|
||||
reinterpret_cast<uintptr_t>(stmt->block));
|
||||
break;
|
||||
case StatementType::Goto:
|
||||
ret += fmt::format("{} if ({}) goto L{};\n", indent, DumpExpr(stmt->cond),
|
||||
stmt->label->id);
|
||||
break;
|
||||
case StatementType::Label:
|
||||
ret += fmt::format("{}L{}:\n", indent, stmt->id);
|
||||
break;
|
||||
case StatementType::If:
|
||||
ret += fmt::format("{} if ({}) {{\n", indent, DumpExpr(stmt->cond));
|
||||
ret += DumpTree(stmt->children, indentation + 4);
|
||||
ret += fmt::format("{} }}\n", indent);
|
||||
break;
|
||||
case StatementType::Loop:
|
||||
ret += fmt::format("{} do {{\n", indent);
|
||||
ret += DumpTree(stmt->children, indentation + 4);
|
||||
ret += fmt::format("{} }} while ({});\n", indent, DumpExpr(stmt->cond));
|
||||
break;
|
||||
case StatementType::Break:
|
||||
ret += fmt::format("{} if ({}) break;\n", indent, DumpExpr(stmt->cond));
|
||||
break;
|
||||
case StatementType::Return:
|
||||
ret += fmt::format("{} return;\n", indent);
|
||||
break;
|
||||
case StatementType::Kill:
|
||||
ret += fmt::format("{} kill;\n", indent);
|
||||
break;
|
||||
case StatementType::Unreachable:
|
||||
ret += fmt::format("{} unreachable;\n", indent);
|
||||
break;
|
||||
case StatementType::SetVariable:
|
||||
ret += fmt::format("{} goto_L{} = {};\n", indent, stmt->id, DumpExpr(stmt->op));
|
||||
break;
|
||||
case StatementType::Function:
|
||||
case StatementType::Identity:
|
||||
case StatementType::Not:
|
||||
case StatementType::Or:
|
||||
case StatementType::Variable:
|
||||
throw LogicError("Statement can't be printed");
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void SanitizeNoBreaks(const Tree& tree) {
|
||||
if (std::ranges::find(tree, StatementType::Break, &Statement::type) != tree.end()) {
|
||||
throw NotImplementedException("Capturing statement with break nodes");
|
||||
}
|
||||
}
|
||||
|
||||
size_t Level(Node stmt) {
|
||||
size_t level{0};
|
||||
Statement* node{stmt->up};
|
||||
while (node) {
|
||||
++level;
|
||||
node = node->up;
|
||||
}
|
||||
return level;
|
||||
}
|
||||
|
||||
bool IsDirectlyRelated(Node goto_stmt, Node label_stmt) {
|
||||
const size_t goto_level{Level(goto_stmt)};
|
||||
const size_t label_level{Level(label_stmt)};
|
||||
size_t min_level;
|
||||
size_t max_level;
|
||||
Node min;
|
||||
Node max;
|
||||
if (label_level < goto_level) {
|
||||
min_level = label_level;
|
||||
max_level = goto_level;
|
||||
min = label_stmt;
|
||||
max = goto_stmt;
|
||||
} else { // goto_level < label_level
|
||||
min_level = goto_level;
|
||||
max_level = label_level;
|
||||
min = goto_stmt;
|
||||
max = label_stmt;
|
||||
}
|
||||
while (max_level > min_level) {
|
||||
--max_level;
|
||||
max = max->up;
|
||||
}
|
||||
return min->up == max->up;
|
||||
}
|
||||
|
||||
bool IsIndirectlyRelated(Node goto_stmt, Node label_stmt) {
|
||||
return goto_stmt->up != label_stmt->up && !IsDirectlyRelated(goto_stmt, label_stmt);
|
||||
}
|
||||
|
||||
[[maybe_unused]] bool AreSiblings(Node goto_stmt, Node label_stmt) noexcept {
|
||||
Node it{goto_stmt};
|
||||
do {
|
||||
if (it == label_stmt) {
|
||||
return true;
|
||||
}
|
||||
--it;
|
||||
} while (it != goto_stmt->up->children.begin());
|
||||
while (it != goto_stmt->up->children.end()) {
|
||||
if (it == label_stmt) {
|
||||
return true;
|
||||
}
|
||||
++it;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
Node SiblingFromNephew(Node uncle, Node nephew) noexcept {
|
||||
Statement* const parent{uncle->up};
|
||||
Statement* it{&*nephew};
|
||||
while (it->up != parent) {
|
||||
it = it->up;
|
||||
}
|
||||
return Tree::s_iterator_to(*it);
|
||||
}
|
||||
|
||||
bool AreOrdered(Node left_sibling, Node right_sibling) noexcept {
|
||||
const Node end{right_sibling->up->children.end()};
|
||||
for (auto it = right_sibling; it != end; ++it) {
|
||||
if (it == left_sibling) {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool NeedsLift(Node goto_stmt, Node label_stmt) noexcept {
|
||||
const Node sibling{SiblingFromNephew(goto_stmt, label_stmt)};
|
||||
return AreOrdered(sibling, goto_stmt);
|
||||
}
|
||||
|
||||
/**
|
||||
* The algorithm used here is from:
|
||||
* Taming Control Flow: A Structured Approach to Eliminating Goto Statements.
|
||||
* Ana M. Erosa and Laurie J. Hendren
|
||||
* http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.42.1485&rep=rep1&type=pdf
|
||||
*/
|
||||
class GotoPass {
|
||||
public:
|
||||
explicit GotoPass(CFG& cfg, ObjectPool<Statement>& stmt_pool) : pool{stmt_pool} {
|
||||
std::vector gotos{BuildTree(cfg)};
|
||||
const auto end{gotos.rend()};
|
||||
for (auto goto_stmt = gotos.rbegin(); goto_stmt != end; ++goto_stmt) {
|
||||
RemoveGoto(*goto_stmt);
|
||||
}
|
||||
}
|
||||
|
||||
Statement& RootStatement() noexcept {
|
||||
return root_stmt;
|
||||
}
|
||||
|
||||
private:
|
||||
void RemoveGoto(Node goto_stmt) {
|
||||
// Force goto_stmt and label_stmt to be directly related
|
||||
const Node label_stmt{goto_stmt->label};
|
||||
if (IsIndirectlyRelated(goto_stmt, label_stmt)) {
|
||||
// Move goto_stmt out using outward-movement transformation until it becomes
|
||||
// directly related to label_stmt
|
||||
while (!IsDirectlyRelated(goto_stmt, label_stmt)) {
|
||||
goto_stmt = MoveOutward(goto_stmt);
|
||||
}
|
||||
}
|
||||
// Force goto_stmt and label_stmt to be siblings
|
||||
if (IsDirectlyRelated(goto_stmt, label_stmt)) {
|
||||
const size_t label_level{Level(label_stmt)};
|
||||
size_t goto_level{Level(goto_stmt)};
|
||||
if (goto_level > label_level) {
|
||||
// Move goto_stmt out of its level using outward-movement transformations
|
||||
while (goto_level > label_level) {
|
||||
goto_stmt = MoveOutward(goto_stmt);
|
||||
--goto_level;
|
||||
}
|
||||
} else { // Level(goto_stmt) < Level(label_stmt)
|
||||
if (NeedsLift(goto_stmt, label_stmt)) {
|
||||
// Lift goto_stmt to above stmt containing label_stmt using goto-lifting
|
||||
// transformations
|
||||
goto_stmt = Lift(goto_stmt);
|
||||
}
|
||||
// Move goto_stmt into label_stmt's level using inward-movement transformation
|
||||
while (goto_level < label_level) {
|
||||
goto_stmt = MoveInward(goto_stmt);
|
||||
++goto_level;
|
||||
}
|
||||
}
|
||||
}
|
||||
// Expensive operation:
|
||||
if (!AreSiblings(goto_stmt, label_stmt)) {
|
||||
throw LogicError("Goto is not a sibling with the label");
|
||||
}
|
||||
// goto_stmt and label_stmt are guaranteed to be siblings, eliminate
|
||||
if (std::next(goto_stmt) == label_stmt) {
|
||||
// Simply eliminate the goto if the label is next to it
|
||||
goto_stmt->up->children.erase(goto_stmt);
|
||||
} else if (AreOrdered(goto_stmt, label_stmt)) {
|
||||
// Eliminate goto_stmt with a conditional
|
||||
EliminateAsConditional(goto_stmt, label_stmt);
|
||||
} else {
|
||||
// Eliminate goto_stmt with a loop
|
||||
EliminateAsLoop(goto_stmt, label_stmt);
|
||||
}
|
||||
}
|
||||
|
||||
std::vector<Node> BuildTree(CFG& cfg) {
|
||||
u32 label_id{0};
|
||||
std::vector<Node> gotos;
|
||||
BuildTree(cfg, label_id, gotos, root_stmt.children.end(), std::nullopt);
|
||||
return gotos;
|
||||
}
|
||||
|
||||
void BuildTree(CFG& cfg, u32& label_id, std::vector<Node>& gotos, Node function_insert_point,
|
||||
std::optional<Node> return_label) {
|
||||
Statement* const false_stmt{pool.Create(Identity{}, IR::Condition::False, &root_stmt)};
|
||||
Tree& root{root_stmt.children};
|
||||
std::unordered_map<Block*, Node> local_labels;
|
||||
local_labels.reserve(cfg.blocks.size());
|
||||
|
||||
for (Block& block : cfg.blocks) {
|
||||
Statement* const label{pool.Create(Label{}, label_id, &root_stmt)};
|
||||
const Node label_it{root.insert(function_insert_point, *label)};
|
||||
local_labels.emplace(&block, label_it);
|
||||
++label_id;
|
||||
}
|
||||
for (Block& block : cfg.blocks) {
|
||||
const Node label{local_labels.at(&block)};
|
||||
// Insertion point
|
||||
const Node ip{std::next(label)};
|
||||
|
||||
// Reset goto variables before the first block and after its respective label
|
||||
const auto make_reset_variable{[&]() -> Statement& {
|
||||
return *pool.Create(SetVariable{}, label->id, false_stmt, &root_stmt);
|
||||
}};
|
||||
root.push_front(make_reset_variable());
|
||||
root.insert(ip, make_reset_variable());
|
||||
root.insert(ip, *pool.Create(&block, &root_stmt));
|
||||
|
||||
switch (block.end_class) {
|
||||
case EndClass::Branch: {
|
||||
Statement* const always_cond{
|
||||
pool.Create(Identity{}, IR::Condition::True, &root_stmt)};
|
||||
if (block.cond == IR::Condition::True) {
|
||||
const Node true_label{local_labels.at(block.branch_true)};
|
||||
gotos.push_back(
|
||||
root.insert(ip, *pool.Create(Goto{}, always_cond, true_label, &root_stmt)));
|
||||
} else if (block.cond == IR::Condition::False) {
|
||||
const Node false_label{local_labels.at(block.branch_false)};
|
||||
gotos.push_back(root.insert(
|
||||
ip, *pool.Create(Goto{}, always_cond, false_label, &root_stmt)));
|
||||
} else {
|
||||
const Node true_label{local_labels.at(block.branch_true)};
|
||||
const Node false_label{local_labels.at(block.branch_false)};
|
||||
Statement* const true_cond{pool.Create(Identity{}, block.cond, &root_stmt)};
|
||||
gotos.push_back(
|
||||
root.insert(ip, *pool.Create(Goto{}, true_cond, true_label, &root_stmt)));
|
||||
gotos.push_back(root.insert(
|
||||
ip, *pool.Create(Goto{}, always_cond, false_label, &root_stmt)));
|
||||
}
|
||||
break;
|
||||
}
|
||||
case EndClass::Exit:
|
||||
root.insert(ip, *pool.Create(Return{}, &root_stmt));
|
||||
break;
|
||||
// case EndClass::Kill:
|
||||
// root.insert(ip, *pool.Create(Kill{}, &root_stmt));
|
||||
// break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void UpdateTreeUp(Statement* tree) {
|
||||
for (Statement& stmt : tree->children) {
|
||||
stmt.up = tree;
|
||||
}
|
||||
}
|
||||
|
||||
void EliminateAsConditional(Node goto_stmt, Node label_stmt) {
|
||||
Tree& body{goto_stmt->up->children};
|
||||
Tree if_body;
|
||||
if_body.splice(if_body.begin(), body, std::next(goto_stmt), label_stmt);
|
||||
Statement* const cond{pool.Create(Not{}, goto_stmt->cond, &root_stmt)};
|
||||
Statement* const if_stmt{pool.Create(If{}, cond, std::move(if_body), goto_stmt->up)};
|
||||
UpdateTreeUp(if_stmt);
|
||||
body.insert(goto_stmt, *if_stmt);
|
||||
body.erase(goto_stmt);
|
||||
}
|
||||
|
||||
void EliminateAsLoop(Node goto_stmt, Node label_stmt) {
|
||||
Tree& body{goto_stmt->up->children};
|
||||
Tree loop_body;
|
||||
loop_body.splice(loop_body.begin(), body, label_stmt, goto_stmt);
|
||||
Statement* const cond{goto_stmt->cond};
|
||||
Statement* const loop{pool.Create(Loop{}, cond, std::move(loop_body), goto_stmt->up)};
|
||||
UpdateTreeUp(loop);
|
||||
body.insert(goto_stmt, *loop);
|
||||
body.erase(goto_stmt);
|
||||
}
|
||||
|
||||
[[nodiscard]] Node MoveOutward(Node goto_stmt) {
|
||||
switch (goto_stmt->up->type) {
|
||||
case StatementType::If:
|
||||
return MoveOutwardIf(goto_stmt);
|
||||
case StatementType::Loop:
|
||||
return MoveOutwardLoop(goto_stmt);
|
||||
default:
|
||||
throw LogicError("Invalid outward movement");
|
||||
}
|
||||
}
|
||||
|
||||
[[nodiscard]] Node MoveInward(Node goto_stmt) {
|
||||
Statement* const parent{goto_stmt->up};
|
||||
Tree& body{parent->children};
|
||||
const Node label{goto_stmt->label};
|
||||
const Node label_nested_stmt{SiblingFromNephew(goto_stmt, label)};
|
||||
const u32 label_id{label->id};
|
||||
|
||||
Statement* const goto_cond{goto_stmt->cond};
|
||||
Statement* const set_var{pool.Create(SetVariable{}, label_id, goto_cond, parent)};
|
||||
body.insert(goto_stmt, *set_var);
|
||||
|
||||
Tree if_body;
|
||||
if_body.splice(if_body.begin(), body, std::next(goto_stmt), label_nested_stmt);
|
||||
Statement* const variable{pool.Create(Variable{}, label_id, &root_stmt)};
|
||||
Statement* const neg_var{pool.Create(Not{}, variable, &root_stmt)};
|
||||
if (!if_body.empty()) {
|
||||
Statement* const if_stmt{pool.Create(If{}, neg_var, std::move(if_body), parent)};
|
||||
UpdateTreeUp(if_stmt);
|
||||
body.insert(goto_stmt, *if_stmt);
|
||||
}
|
||||
body.erase(goto_stmt);
|
||||
|
||||
switch (label_nested_stmt->type) {
|
||||
case StatementType::If:
|
||||
// Update nested if condition
|
||||
label_nested_stmt->cond =
|
||||
pool.Create(Or{}, variable, label_nested_stmt->cond, &root_stmt);
|
||||
break;
|
||||
case StatementType::Loop:
|
||||
break;
|
||||
default:
|
||||
throw LogicError("Invalid inward movement");
|
||||
}
|
||||
Tree& nested_tree{label_nested_stmt->children};
|
||||
Statement* const new_goto{pool.Create(Goto{}, variable, label, &*label_nested_stmt)};
|
||||
return nested_tree.insert(nested_tree.begin(), *new_goto);
|
||||
}
|
||||
|
||||
[[nodiscard]] Node Lift(Node goto_stmt) {
|
||||
Statement* const parent{goto_stmt->up};
|
||||
Tree& body{parent->children};
|
||||
const Node label{goto_stmt->label};
|
||||
const u32 label_id{label->id};
|
||||
const Node label_nested_stmt{SiblingFromNephew(goto_stmt, label)};
|
||||
|
||||
Tree loop_body;
|
||||
loop_body.splice(loop_body.begin(), body, label_nested_stmt, goto_stmt);
|
||||
SanitizeNoBreaks(loop_body);
|
||||
Statement* const variable{pool.Create(Variable{}, label_id, &root_stmt)};
|
||||
Statement* const loop_stmt{pool.Create(Loop{}, variable, std::move(loop_body), parent)};
|
||||
UpdateTreeUp(loop_stmt);
|
||||
body.insert(goto_stmt, *loop_stmt);
|
||||
|
||||
Statement* const new_goto{pool.Create(Goto{}, variable, label, loop_stmt)};
|
||||
loop_stmt->children.push_front(*new_goto);
|
||||
const Node new_goto_node{loop_stmt->children.begin()};
|
||||
|
||||
Statement* const set_var{pool.Create(SetVariable{}, label_id, goto_stmt->cond, loop_stmt)};
|
||||
loop_stmt->children.push_back(*set_var);
|
||||
|
||||
body.erase(goto_stmt);
|
||||
return new_goto_node;
|
||||
}
|
||||
|
||||
Node MoveOutwardIf(Node goto_stmt) {
|
||||
const Node parent{Tree::s_iterator_to(*goto_stmt->up)};
|
||||
Tree& body{parent->children};
|
||||
const u32 label_id{goto_stmt->label->id};
|
||||
Statement* const goto_cond{goto_stmt->cond};
|
||||
Statement* const set_goto_var{pool.Create(SetVariable{}, label_id, goto_cond, &*parent)};
|
||||
body.insert(goto_stmt, *set_goto_var);
|
||||
|
||||
Tree if_body;
|
||||
if_body.splice(if_body.begin(), body, std::next(goto_stmt), body.end());
|
||||
if_body.pop_front();
|
||||
Statement* const cond{pool.Create(Variable{}, label_id, &root_stmt)};
|
||||
Statement* const neg_cond{pool.Create(Not{}, cond, &root_stmt)};
|
||||
Statement* const if_stmt{pool.Create(If{}, neg_cond, std::move(if_body), &*parent)};
|
||||
UpdateTreeUp(if_stmt);
|
||||
body.insert(goto_stmt, *if_stmt);
|
||||
|
||||
body.erase(goto_stmt);
|
||||
|
||||
Statement* const new_cond{pool.Create(Variable{}, label_id, &root_stmt)};
|
||||
Statement* const new_goto{pool.Create(Goto{}, new_cond, goto_stmt->label, parent->up)};
|
||||
Tree& parent_tree{parent->up->children};
|
||||
return parent_tree.insert(std::next(parent), *new_goto);
|
||||
}
|
||||
|
||||
Node MoveOutwardLoop(Node goto_stmt) {
|
||||
Statement* const parent{goto_stmt->up};
|
||||
Tree& body{parent->children};
|
||||
const u32 label_id{goto_stmt->label->id};
|
||||
Statement* const goto_cond{goto_stmt->cond};
|
||||
Statement* const set_goto_var{pool.Create(SetVariable{}, label_id, goto_cond, parent)};
|
||||
Statement* const cond{pool.Create(Variable{}, label_id, &root_stmt)};
|
||||
Statement* const break_stmt{pool.Create(Break{}, cond, parent)};
|
||||
body.insert(goto_stmt, *set_goto_var);
|
||||
body.insert(goto_stmt, *break_stmt);
|
||||
body.erase(goto_stmt);
|
||||
|
||||
const Node loop{Tree::s_iterator_to(*goto_stmt->up)};
|
||||
Statement* const new_goto_cond{pool.Create(Variable{}, label_id, &root_stmt)};
|
||||
Statement* const new_goto{pool.Create(Goto{}, new_goto_cond, goto_stmt->label, loop->up)};
|
||||
Tree& parent_tree{loop->up->children};
|
||||
return parent_tree.insert(std::next(loop), *new_goto);
|
||||
}
|
||||
|
||||
ObjectPool<Statement>& pool;
|
||||
Statement root_stmt{FunctionTag{}};
|
||||
};
|
||||
|
||||
[[nodiscard]] Statement* TryFindForwardBlock(Statement& stmt) {
|
||||
Tree& tree{stmt.up->children};
|
||||
const Node end{tree.end()};
|
||||
Node forward_node{std::next(Tree::s_iterator_to(stmt))};
|
||||
while (forward_node != end && !HasChildren(forward_node->type)) {
|
||||
if (forward_node->type == StatementType::Code) {
|
||||
return &*forward_node;
|
||||
}
|
||||
++forward_node;
|
||||
}
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
[[nodiscard]] IR::U1 VisitExpr(IR::IREmitter& ir, const Statement& stmt) {
|
||||
switch (stmt.type) {
|
||||
case StatementType::Identity:
|
||||
return ir.Condition(stmt.guest_cond);
|
||||
case StatementType::Not:
|
||||
return ir.LogicalNot(IR::U1{VisitExpr(ir, *stmt.op)});
|
||||
case StatementType::Or:
|
||||
return ir.LogicalOr(VisitExpr(ir, *stmt.op_a), VisitExpr(ir, *stmt.op_b));
|
||||
case StatementType::Variable:
|
||||
return ir.GetGotoVariable(stmt.id);
|
||||
default:
|
||||
throw NotImplementedException("Statement type {}", u32(stmt.type));
|
||||
}
|
||||
}
|
||||
|
||||
class TranslatePass {
|
||||
public:
|
||||
TranslatePass(ObjectPool<IR::Inst>& inst_pool_, ObjectPool<IR::Block>& block_pool_,
|
||||
ObjectPool<Statement>& stmt_pool_, Statement& root_stmt,
|
||||
IR::AbstractSyntaxList& syntax_list_, std::span<const GcnInst> inst_list_,
|
||||
Stage stage_)
|
||||
: stmt_pool{stmt_pool_}, inst_pool{inst_pool_}, block_pool{block_pool_},
|
||||
syntax_list{syntax_list_}, inst_list{inst_list_}, stage{stage_} {
|
||||
Visit(root_stmt, nullptr, nullptr);
|
||||
|
||||
IR::Block& first_block{*syntax_list.front().data.block};
|
||||
IR::IREmitter ir(first_block, first_block.begin());
|
||||
ir.Prologue();
|
||||
}
|
||||
|
||||
private:
|
||||
void Visit(Statement& parent, IR::Block* break_block, IR::Block* fallthrough_block) {
|
||||
IR::Block* current_block{};
|
||||
const auto ensure_block{[&] {
|
||||
if (current_block) {
|
||||
return;
|
||||
}
|
||||
current_block = block_pool.Create(inst_pool);
|
||||
auto& node{syntax_list.emplace_back()};
|
||||
node.type = IR::AbstractSyntaxNode::Type::Block;
|
||||
node.data.block = current_block;
|
||||
}};
|
||||
Tree& tree{parent.children};
|
||||
for (auto it = tree.begin(); it != tree.end(); ++it) {
|
||||
Statement& stmt{*it};
|
||||
switch (stmt.type) {
|
||||
case StatementType::Label:
|
||||
// Labels can be ignored
|
||||
break;
|
||||
case StatementType::Code: {
|
||||
ensure_block();
|
||||
const u32 start = stmt.block->begin_index;
|
||||
const u32 size = stmt.block->end_index - start + 1;
|
||||
Translate(current_block, stage, inst_list.subspan(start, size));
|
||||
fmt::print("{}\n", IR::DumpBlock(*current_block));
|
||||
break;
|
||||
}
|
||||
case StatementType::SetVariable: {
|
||||
ensure_block();
|
||||
IR::IREmitter ir{*current_block};
|
||||
ir.SetGotoVariable(stmt.id, VisitExpr(ir, *stmt.op));
|
||||
break;
|
||||
}
|
||||
case StatementType::If: {
|
||||
ensure_block();
|
||||
IR::Block* const merge_block{MergeBlock(parent, stmt)};
|
||||
|
||||
// Implement if header block
|
||||
IR::IREmitter ir{*current_block};
|
||||
const IR::U1 cond{ir.ConditionRef(VisitExpr(ir, *stmt.cond))};
|
||||
|
||||
const size_t if_node_index{syntax_list.size()};
|
||||
syntax_list.emplace_back();
|
||||
|
||||
// Visit children
|
||||
const size_t then_block_index{syntax_list.size()};
|
||||
Visit(stmt, break_block, merge_block);
|
||||
|
||||
IR::Block* const then_block{syntax_list.at(then_block_index).data.block};
|
||||
current_block->AddBranch(then_block);
|
||||
current_block->AddBranch(merge_block);
|
||||
current_block = merge_block;
|
||||
|
||||
auto& if_node{syntax_list[if_node_index]};
|
||||
if_node.type = IR::AbstractSyntaxNode::Type::If;
|
||||
if_node.data.if_node.cond = cond;
|
||||
if_node.data.if_node.body = then_block;
|
||||
if_node.data.if_node.merge = merge_block;
|
||||
|
||||
auto& endif_node{syntax_list.emplace_back()};
|
||||
endif_node.type = IR::AbstractSyntaxNode::Type::EndIf;
|
||||
endif_node.data.end_if.merge = merge_block;
|
||||
|
||||
auto& merge{syntax_list.emplace_back()};
|
||||
merge.type = IR::AbstractSyntaxNode::Type::Block;
|
||||
merge.data.block = merge_block;
|
||||
break;
|
||||
}
|
||||
case StatementType::Loop: {
|
||||
IR::Block* const loop_header_block{block_pool.Create(inst_pool)};
|
||||
if (current_block) {
|
||||
current_block->AddBranch(loop_header_block);
|
||||
}
|
||||
auto& header_node{syntax_list.emplace_back()};
|
||||
header_node.type = IR::AbstractSyntaxNode::Type::Block;
|
||||
header_node.data.block = loop_header_block;
|
||||
|
||||
IR::Block* const continue_block{block_pool.Create(inst_pool)};
|
||||
IR::Block* const merge_block{MergeBlock(parent, stmt)};
|
||||
|
||||
const size_t loop_node_index{syntax_list.size()};
|
||||
syntax_list.emplace_back();
|
||||
|
||||
// Visit children
|
||||
const size_t body_block_index{syntax_list.size()};
|
||||
Visit(stmt, merge_block, continue_block);
|
||||
|
||||
// The continue block is located at the end of the loop
|
||||
IR::IREmitter ir{*continue_block};
|
||||
const IR::U1 cond{ir.ConditionRef(VisitExpr(ir, *stmt.cond))};
|
||||
|
||||
IR::Block* const body_block{syntax_list.at(body_block_index).data.block};
|
||||
loop_header_block->AddBranch(body_block);
|
||||
|
||||
continue_block->AddBranch(loop_header_block);
|
||||
continue_block->AddBranch(merge_block);
|
||||
|
||||
current_block = merge_block;
|
||||
|
||||
auto& loop{syntax_list[loop_node_index]};
|
||||
loop.type = IR::AbstractSyntaxNode::Type::Loop;
|
||||
loop.data.loop.body = body_block;
|
||||
loop.data.loop.continue_block = continue_block;
|
||||
loop.data.loop.merge = merge_block;
|
||||
|
||||
auto& continue_block_node{syntax_list.emplace_back()};
|
||||
continue_block_node.type = IR::AbstractSyntaxNode::Type::Block;
|
||||
continue_block_node.data.block = continue_block;
|
||||
|
||||
auto& repeat{syntax_list.emplace_back()};
|
||||
repeat.type = IR::AbstractSyntaxNode::Type::Repeat;
|
||||
repeat.data.repeat.cond = cond;
|
||||
repeat.data.repeat.loop_header = loop_header_block;
|
||||
repeat.data.repeat.merge = merge_block;
|
||||
|
||||
auto& merge{syntax_list.emplace_back()};
|
||||
merge.type = IR::AbstractSyntaxNode::Type::Block;
|
||||
merge.data.block = merge_block;
|
||||
break;
|
||||
}
|
||||
case StatementType::Break: {
|
||||
ensure_block();
|
||||
IR::Block* const skip_block{MergeBlock(parent, stmt)};
|
||||
|
||||
IR::IREmitter ir{*current_block};
|
||||
const IR::U1 cond{ir.ConditionRef(VisitExpr(ir, *stmt.cond))};
|
||||
current_block->AddBranch(break_block);
|
||||
current_block->AddBranch(skip_block);
|
||||
current_block = skip_block;
|
||||
|
||||
auto& break_node{syntax_list.emplace_back()};
|
||||
break_node.type = IR::AbstractSyntaxNode::Type::Break;
|
||||
break_node.data.break_node.cond = cond;
|
||||
break_node.data.break_node.merge = break_block;
|
||||
break_node.data.break_node.skip = skip_block;
|
||||
|
||||
auto& merge{syntax_list.emplace_back()};
|
||||
merge.type = IR::AbstractSyntaxNode::Type::Block;
|
||||
merge.data.block = skip_block;
|
||||
break;
|
||||
}
|
||||
case StatementType::Return: {
|
||||
ensure_block();
|
||||
IR::Block* return_block{block_pool.Create(inst_pool)};
|
||||
IR::IREmitter{*return_block}.Epilogue();
|
||||
current_block->AddBranch(return_block);
|
||||
|
||||
auto& merge{syntax_list.emplace_back()};
|
||||
merge.type = IR::AbstractSyntaxNode::Type::Block;
|
||||
merge.data.block = return_block;
|
||||
|
||||
current_block = nullptr;
|
||||
syntax_list.emplace_back().type = IR::AbstractSyntaxNode::Type::Return;
|
||||
break;
|
||||
}
|
||||
case StatementType::Kill: {
|
||||
ensure_block();
|
||||
IR::Block* demote_block{MergeBlock(parent, stmt)};
|
||||
// IR::IREmitter{*current_block}.DemoteToHelperInvocation();
|
||||
current_block->AddBranch(demote_block);
|
||||
current_block = demote_block;
|
||||
|
||||
auto& merge{syntax_list.emplace_back()};
|
||||
merge.type = IR::AbstractSyntaxNode::Type::Block;
|
||||
merge.data.block = demote_block;
|
||||
break;
|
||||
}
|
||||
case StatementType::Unreachable: {
|
||||
ensure_block();
|
||||
current_block = nullptr;
|
||||
syntax_list.emplace_back().type = IR::AbstractSyntaxNode::Type::Unreachable;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
throw NotImplementedException("Statement type {}", u32(stmt.type));
|
||||
}
|
||||
}
|
||||
if (current_block) {
|
||||
if (fallthrough_block) {
|
||||
current_block->AddBranch(fallthrough_block);
|
||||
} else {
|
||||
syntax_list.emplace_back().type = IR::AbstractSyntaxNode::Type::Unreachable;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
IR::Block* MergeBlock(Statement& parent, Statement& stmt) {
|
||||
Statement* merge_stmt{TryFindForwardBlock(stmt)};
|
||||
if (!merge_stmt) {
|
||||
// Create a merge block we can visit later
|
||||
merge_stmt = stmt_pool.Create(&dummy_flow_block, &parent);
|
||||
parent.children.insert(std::next(Tree::s_iterator_to(stmt)), *merge_stmt);
|
||||
}
|
||||
return block_pool.Create(inst_pool);
|
||||
}
|
||||
|
||||
ObjectPool<Statement>& stmt_pool;
|
||||
ObjectPool<IR::Inst>& inst_pool;
|
||||
ObjectPool<IR::Block>& block_pool;
|
||||
IR::AbstractSyntaxList& syntax_list;
|
||||
const Block dummy_flow_block{};
|
||||
std::span<const GcnInst> inst_list;
|
||||
Stage stage;
|
||||
};
|
||||
} // Anonymous namespace
|
||||
|
||||
IR::AbstractSyntaxList BuildASL(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Block>& block_pool,
|
||||
CFG& cfg, Stage stage) {
|
||||
ObjectPool<Statement> stmt_pool{64};
|
||||
GotoPass goto_pass{cfg, stmt_pool};
|
||||
Statement& root{goto_pass.RootStatement()};
|
||||
IR::AbstractSyntaxList syntax_list;
|
||||
TranslatePass{inst_pool, block_pool, stmt_pool, root, syntax_list, cfg.inst_list, stage};
|
||||
return syntax_list;
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
22
src/shader_recompiler/frontend/structured_control_flow.h
Normal file
22
src/shader_recompiler/frontend/structured_control_flow.h
Normal file
|
@ -0,0 +1,22 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "shader_recompiler/frontend/control_flow_graph.h"
|
||||
#include "shader_recompiler/ir/abstract_syntax_list.h"
|
||||
#include "shader_recompiler/ir/basic_block.h"
|
||||
#include "shader_recompiler/ir/value.h"
|
||||
#include "shader_recompiler/object_pool.h"
|
||||
|
||||
namespace Shader {
|
||||
enum class Stage : u32;
|
||||
}
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
[[nodiscard]] IR::AbstractSyntaxList BuildASL(ObjectPool<IR::Inst>& inst_pool,
|
||||
ObjectPool<IR::Block>& block_pool, CFG& cfg,
|
||||
Stage stage);
|
||||
|
||||
} // namespace Shader::Gcn
|
44
src/shader_recompiler/frontend/translate/data_share.cpp
Normal file
44
src/shader_recompiler/frontend/translate/data_share.cpp
Normal file
|
@ -0,0 +1,44 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
void Translator::DS_READ(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst) {
|
||||
const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
if (is_pair) {
|
||||
const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
|
||||
ir.SetVectorReg(dst_reg, ir.ReadShared(32, is_signed, addr0));
|
||||
const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1)));
|
||||
ir.SetVectorReg(dst_reg + 1, ir.ReadShared(32, is_signed, addr1));
|
||||
} else if (bit_size == 64) {
|
||||
const IR::Value data = ir.UnpackUint2x32(ir.ReadShared(bit_size, is_signed, addr));
|
||||
ir.SetVectorReg(dst_reg, IR::U32{ir.CompositeExtract(data, 0)});
|
||||
ir.SetVectorReg(dst_reg + 1, IR::U32{ir.CompositeExtract(data, 1)});
|
||||
} else {
|
||||
const IR::U32 data = ir.ReadShared(bit_size, is_signed, addr);
|
||||
ir.SetVectorReg(dst_reg, data);
|
||||
}
|
||||
}
|
||||
|
||||
void Translator::DS_WRITE(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst) {
|
||||
const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
|
||||
const IR::VectorReg data0{inst.src[1].code};
|
||||
const IR::VectorReg data1{inst.src[2].code};
|
||||
if (is_pair) {
|
||||
const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
|
||||
ir.WriteShared(32, ir.GetVectorReg(data0), addr0);
|
||||
const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1)));
|
||||
ir.WriteShared(32, ir.GetVectorReg(data1), addr1);
|
||||
} else if (bit_size == 64) {
|
||||
const IR::U64 data = ir.PackUint2x32(
|
||||
ir.CompositeConstruct(ir.GetVectorReg(data0), ir.GetVectorReg(data0 + 1)));
|
||||
ir.WriteShared(bit_size, data, addr);
|
||||
} else {
|
||||
ir.WriteShared(bit_size, ir.GetVectorReg(data0), addr);
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
49
src/shader_recompiler/frontend/translate/export.cpp
Normal file
49
src/shader_recompiler/frontend/translate/export.cpp
Normal file
|
@ -0,0 +1,49 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
void Translator::EXP(const GcnInst& inst) {
|
||||
const auto& exp = inst.control.exp;
|
||||
const IR::Attribute attrib{exp.target};
|
||||
const std::array vsrc = {
|
||||
IR::VectorReg(inst.src[0].code),
|
||||
IR::VectorReg(inst.src[1].code),
|
||||
IR::VectorReg(inst.src[2].code),
|
||||
IR::VectorReg(inst.src[3].code),
|
||||
};
|
||||
|
||||
const auto unpack = [&](u32 idx) {
|
||||
const IR::Value value = ir.UnpackHalf2x16(ir.GetVectorReg(vsrc[idx]));
|
||||
const IR::F32 r = IR::F32{ir.CompositeExtract(value, 0)};
|
||||
const IR::F32 g = IR::F32{ir.CompositeExtract(value, 1)};
|
||||
ir.SetAttribute(attrib, r, idx * 2);
|
||||
ir.SetAttribute(attrib, g, idx * 2 + 1);
|
||||
};
|
||||
|
||||
// Components are float16 packed into a VGPR
|
||||
if (exp.compr) {
|
||||
// Export R, G
|
||||
if (exp.en & 1) {
|
||||
unpack(0);
|
||||
}
|
||||
// Export B, A
|
||||
if ((exp.en >> 2) & 1) {
|
||||
unpack(1);
|
||||
}
|
||||
} else {
|
||||
// Components are float32 into separate VGPRS
|
||||
u32 mask = exp.en;
|
||||
for (u32 i = 0; i < 4; i++, mask >>= 1) {
|
||||
if ((mask & 1) == 0) {
|
||||
continue;
|
||||
}
|
||||
const IR::F32 comp = ir.GetVectorReg<IR::F32>(vsrc[i]);
|
||||
ir.SetAttribute(attrib, comp, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
0
src/shader_recompiler/frontend/translate/flat_memory.cpp
Normal file
0
src/shader_recompiler/frontend/translate/flat_memory.cpp
Normal file
38
src/shader_recompiler/frontend/translate/scalar_alu.cpp
Normal file
38
src/shader_recompiler/frontend/translate/scalar_alu.cpp
Normal file
|
@ -0,0 +1,38 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
void Translator::S_MOV(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], GetSrc(inst.src[0]));
|
||||
}
|
||||
|
||||
void Translator::S_MUL_I32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], ir.IMul(GetSrc(inst.src[0]), GetSrc(inst.src[1])));
|
||||
}
|
||||
|
||||
void Translator::S_CMP(ConditionOp cond, bool is_signed, const GcnInst& inst) {
|
||||
const IR::U32 lhs = GetSrc(inst.src[0]);
|
||||
const IR::U32 rhs = GetSrc(inst.src[1]);
|
||||
const IR::U1 result = [&] {
|
||||
switch (cond) {
|
||||
case ConditionOp::EQ:
|
||||
return ir.IEqual(lhs, rhs);
|
||||
case ConditionOp::LG:
|
||||
return ir.INotEqual(lhs, rhs);
|
||||
case ConditionOp::GT:
|
||||
return ir.IGreaterThan(lhs, rhs, is_signed);
|
||||
case ConditionOp::GE:
|
||||
return ir.IGreaterThanEqual(lhs, rhs, is_signed);
|
||||
case ConditionOp::LT:
|
||||
return ir.ILessThan(lhs, rhs, is_signed);
|
||||
case ConditionOp::LE:
|
||||
return ir.ILessThanEqual(lhs, rhs, is_signed);
|
||||
}
|
||||
}();
|
||||
// ir.SetScc(result);
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
45
src/shader_recompiler/frontend/translate/scalar_memory.cpp
Normal file
45
src/shader_recompiler/frontend/translate/scalar_memory.cpp
Normal file
|
@ -0,0 +1,45 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
void Load(IR::IREmitter& ir, int num_dwords, const IR::Value& handle, IR::ScalarReg dst_reg,
|
||||
const IR::U32U64& address) {
|
||||
for (u32 i = 0; i < num_dwords; i++) {
|
||||
const IR::U32 value = handle.IsEmpty() ? ir.ReadConst(address, ir.Imm32(i))
|
||||
: ir.ReadConstBuffer(handle, address, ir.Imm32(i));
|
||||
ir.SetScalarReg(dst_reg++, value);
|
||||
}
|
||||
}
|
||||
|
||||
void Translator::S_LOAD_DWORD(int num_dwords, const GcnInst& inst) {
|
||||
const auto& smrd = inst.control.smrd;
|
||||
const IR::ScalarReg sbase = IR::ScalarReg(inst.src[0].code * 2);
|
||||
const IR::U32 offset =
|
||||
smrd.imm ? ir.Imm32(smrd.offset * 4)
|
||||
: IR::U32{ir.ShiftLeftLogical(ir.GetScalarReg(IR::ScalarReg(smrd.offset)),
|
||||
ir.Imm32(2))};
|
||||
const IR::U64 base =
|
||||
ir.PackUint2x32(ir.CompositeConstruct(ir.GetScalarReg(sbase), ir.GetScalarReg(sbase + 1)));
|
||||
const IR::U64 address = ir.IAdd(base, offset);
|
||||
const IR::ScalarReg dst_reg{inst.dst[0].code};
|
||||
Load(ir, num_dwords, {}, dst_reg, address);
|
||||
}
|
||||
|
||||
void Translator::S_BUFFER_LOAD_DWORD(int num_dwords, const GcnInst& inst) {
|
||||
const auto& smrd = inst.control.smrd;
|
||||
const IR::ScalarReg sbase = IR::ScalarReg(inst.src[0].code * 2);
|
||||
const IR::U32 offset =
|
||||
smrd.imm ? ir.Imm32(smrd.offset * 4)
|
||||
: IR::U32{ir.ShiftLeftLogical(ir.GetScalarReg(IR::ScalarReg(smrd.offset)),
|
||||
ir.Imm32(2))};
|
||||
const IR::Value vsharp =
|
||||
ir.CompositeConstruct(ir.GetScalarReg(sbase), ir.GetScalarReg(sbase + 1),
|
||||
ir.GetScalarReg(sbase + 2), ir.GetScalarReg(sbase + 3));
|
||||
const IR::ScalarReg dst_reg{inst.dst[0].code};
|
||||
Load(ir, num_dwords, vsharp, dst_reg, offset);
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
152
src/shader_recompiler/frontend/translate/translate.cpp
Normal file
152
src/shader_recompiler/frontend/translate/translate.cpp
Normal file
|
@ -0,0 +1,152 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "shader_recompiler/exception.h"
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
#include "shader_recompiler/runtime_info.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
Translator::Translator(IR::Block* block_, Stage stage) : block{block_}, ir{*block} {
|
||||
IR::VectorReg dst_vreg = IR::VectorReg::V0;
|
||||
switch (stage) {
|
||||
case Stage::Vertex:
|
||||
// https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L146C1-L146C23
|
||||
ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
|
||||
ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId));
|
||||
ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::PrimitiveId));
|
||||
break;
|
||||
case Stage::Fragment:
|
||||
// https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L258
|
||||
// The first two VGPRs are used for i/j barycentric coordinates. In the vast majority of
|
||||
// cases it will be only those two, but if shader is using both e.g linear and perspective
|
||||
// inputs it can be more For now assume that this isn't the case.
|
||||
dst_vreg = IR::VectorReg::V2;
|
||||
for (u32 i = 0; i < 4; i++) {
|
||||
ir.SetVectorReg(dst_vreg++, ir.GetAttribute(IR::Attribute::FragCoord, i));
|
||||
}
|
||||
ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::IsFrontFace));
|
||||
break;
|
||||
default:
|
||||
throw NotImplementedException("Unknown shader stage");
|
||||
}
|
||||
|
||||
// Initialize user data.
|
||||
IR::ScalarReg dst_sreg = IR::ScalarReg::S0;
|
||||
for (u32 i = 0; i < 16; i++) {
|
||||
ir.SetScalarReg(dst_sreg++, ir.Imm32(0U));
|
||||
}
|
||||
}
|
||||
|
||||
IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
|
||||
switch (operand.field) {
|
||||
case OperandField::ScalarGPR:
|
||||
if (operand.type == ScalarType::Float32 || force_flt) {
|
||||
return ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
|
||||
} else {
|
||||
return ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
|
||||
}
|
||||
case OperandField::VectorGPR:
|
||||
if (operand.type == ScalarType::Float32 || force_flt) {
|
||||
return ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
|
||||
} else {
|
||||
return ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
|
||||
}
|
||||
case OperandField::ConstZero:
|
||||
if (force_flt) {
|
||||
return ir.Imm32(0.f);
|
||||
} else {
|
||||
return ir.Imm32(0U);
|
||||
}
|
||||
case OperandField::SignedConstIntPos:
|
||||
ASSERT(!force_flt);
|
||||
return ir.Imm32(operand.code - SignedConstIntPosMin + 1);
|
||||
case OperandField::SignedConstIntNeg:
|
||||
ASSERT(!force_flt);
|
||||
return ir.Imm32(-s32(operand.code) + SignedConstIntNegMin - 1);
|
||||
case OperandField::LiteralConst:
|
||||
ASSERT(!force_flt);
|
||||
return ir.Imm32(operand.code);
|
||||
case OperandField::ConstFloatPos_1_0:
|
||||
return ir.Imm32(1.f);
|
||||
case OperandField::ConstFloatPos_0_5:
|
||||
return ir.Imm32(0.5f);
|
||||
case OperandField::ConstFloatNeg_0_5:
|
||||
return ir.Imm32(-0.5f);
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
||||
void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
|
||||
switch (operand.field) {
|
||||
case OperandField::ScalarGPR:
|
||||
return ir.SetScalarReg(IR::ScalarReg(operand.code), value);
|
||||
case OperandField::VectorGPR:
|
||||
return ir.SetVectorReg(IR::VectorReg(operand.code), value);
|
||||
case OperandField::VccHi:
|
||||
case OperandField::M0:
|
||||
break; // Ignore for now
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
||||
void Translate(IR::Block* block, Stage stage, std::span<const GcnInst> inst_list) {
|
||||
if (inst_list.empty()) {
|
||||
return;
|
||||
}
|
||||
Translator translator{block, stage};
|
||||
for (const auto& inst : inst_list) {
|
||||
switch (inst.opcode) {
|
||||
case Opcode::S_MOV_B32:
|
||||
translator.S_MOV(inst);
|
||||
break;
|
||||
case Opcode::S_MUL_I32:
|
||||
translator.S_MUL_I32(inst);
|
||||
break;
|
||||
case Opcode::V_MOV_B32:
|
||||
translator.V_MOV(inst);
|
||||
break;
|
||||
case Opcode::V_MAC_F32:
|
||||
translator.V_MAC_F32(inst);
|
||||
break;
|
||||
case Opcode::V_MUL_F32:
|
||||
translator.V_MUL_F32(inst);
|
||||
break;
|
||||
case Opcode::S_SWAPPC_B64:
|
||||
case Opcode::S_WAITCNT:
|
||||
break; // Ignore for now.
|
||||
case Opcode::S_BUFFER_LOAD_DWORDX16:
|
||||
translator.S_BUFFER_LOAD_DWORD(16, inst);
|
||||
break;
|
||||
case Opcode::EXP:
|
||||
translator.EXP(inst);
|
||||
break;
|
||||
case Opcode::V_INTERP_P2_F32:
|
||||
translator.V_INTERP_P2_F32(inst);
|
||||
break;
|
||||
case Opcode::V_CVT_PKRTZ_F16_F32:
|
||||
translator.V_CVT_PKRTZ_F16_F32(inst);
|
||||
break;
|
||||
case Opcode::IMAGE_SAMPLE:
|
||||
translator.IMAGE_SAMPLE(inst);
|
||||
break;
|
||||
case Opcode::V_CMP_EQ_U32:
|
||||
translator.V_CMP_EQ_U32(inst);
|
||||
break;
|
||||
case Opcode::V_CNDMASK_B32:
|
||||
translator.V_CNDMASK_B32(inst);
|
||||
break;
|
||||
case Opcode::S_MOV_B64:
|
||||
case Opcode::S_WQM_B64:
|
||||
case Opcode::V_INTERP_P1_F32:
|
||||
case Opcode::S_ENDPGM:
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE_MSG("Unknown opcode {}", u32(inst.opcode));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
73
src/shader_recompiler/frontend/translate/translate.h
Normal file
73
src/shader_recompiler/frontend/translate/translate.h
Normal file
|
@ -0,0 +1,73 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <span>
|
||||
#include "shader_recompiler/frontend/instruction.h"
|
||||
#include "shader_recompiler/ir/basic_block.h"
|
||||
#include "shader_recompiler/ir/ir_emitter.h"
|
||||
|
||||
namespace Shader {
|
||||
enum class Stage : u32;
|
||||
}
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
enum class ConditionOp : u32 {
|
||||
EQ,
|
||||
LG,
|
||||
GT,
|
||||
GE,
|
||||
LT,
|
||||
LE,
|
||||
};
|
||||
|
||||
class Translator {
|
||||
public:
|
||||
explicit Translator(IR::Block* block_, Stage stage);
|
||||
|
||||
// Scalar ALU
|
||||
void S_MOV(const GcnInst& inst);
|
||||
void S_MUL_I32(const GcnInst& inst);
|
||||
void S_CMP(ConditionOp cond, bool is_signed, const GcnInst& inst);
|
||||
|
||||
// Scalar Memory
|
||||
void S_LOAD_DWORD(int num_dwords, const GcnInst& inst);
|
||||
void S_BUFFER_LOAD_DWORD(int num_dwords, const GcnInst& inst);
|
||||
|
||||
// Vector ALU
|
||||
void V_MOV(const GcnInst& inst);
|
||||
void V_SAD(const GcnInst& inst);
|
||||
void V_MAC_F32(const GcnInst& inst);
|
||||
void V_CVT_PKRTZ_F16_F32(const GcnInst& inst);
|
||||
void V_MUL_F32(const GcnInst& inst);
|
||||
void V_CMP_EQ_U32(const GcnInst& inst);
|
||||
void V_CNDMASK_B32(const GcnInst& inst);
|
||||
|
||||
// Vector interpolation
|
||||
void V_INTERP_P2_F32(const GcnInst& inst);
|
||||
|
||||
// Data share
|
||||
void DS_READ(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst);
|
||||
void DS_WRITE(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst);
|
||||
|
||||
// MIMG
|
||||
void IMAGE_GET_RESINFO(const GcnInst& inst);
|
||||
void IMAGE_SAMPLE(const GcnInst& inst);
|
||||
|
||||
// Export
|
||||
void EXP(const GcnInst& inst);
|
||||
|
||||
private:
|
||||
IR::U32F32 GetSrc(const InstOperand& operand, bool flt_zero = false);
|
||||
void SetDst(const InstOperand& operand, const IR::U32F32& value);
|
||||
|
||||
private:
|
||||
IR::Block* block;
|
||||
IR::IREmitter ir;
|
||||
};
|
||||
|
||||
void Translate(IR::Block* block, Stage stage, std::span<const GcnInst> inst_list);
|
||||
|
||||
} // namespace Shader::Gcn
|
65
src/shader_recompiler/frontend/translate/vector_alu.cpp
Normal file
65
src/shader_recompiler/frontend/translate/vector_alu.cpp
Normal file
|
@ -0,0 +1,65 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
#pragma clang optimize off
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
void Translator::V_MOV(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], GetSrc(inst.src[0]));
|
||||
}
|
||||
|
||||
void Translator::V_SAD(const GcnInst& inst) {
|
||||
const IR::U32 abs_diff = ir.IAbs(ir.ISub(GetSrc(inst.src[0]), GetSrc(inst.src[1])));
|
||||
SetDst(inst.dst[0], ir.IAdd(abs_diff, GetSrc(inst.src[2])));
|
||||
}
|
||||
|
||||
void Translator::V_MAC_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], ir.FPFma(GetSrc(inst.src[0]), GetSrc(inst.src[1]), GetSrc(inst.dst[0])));
|
||||
}
|
||||
|
||||
void Translator::V_CVT_PKRTZ_F16_F32(const GcnInst& inst) {
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
const IR::Value vec_f32 = ir.CompositeConstruct(ir.FPConvert(16, GetSrc(inst.src[0])),
|
||||
ir.FPConvert(16, GetSrc(inst.src[1])));
|
||||
ir.SetVectorReg(dst_reg, ir.PackFloat2x16(vec_f32));
|
||||
}
|
||||
|
||||
void Translator::V_MUL_F32(const GcnInst& inst) {
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
ir.SetVectorReg(dst_reg, ir.FPMul(GetSrc(inst.src[0]), GetSrc(inst.src[1])));
|
||||
}
|
||||
|
||||
void Translator::V_CMP_EQ_U32(const GcnInst& inst) {
|
||||
const IR::U1 result = ir.IEqual(GetSrc(inst.src[0]), GetSrc(inst.src[1]));
|
||||
if (inst.dst[1].field == OperandField::VccLo) {
|
||||
return ir.SetVcc(result);
|
||||
} else if (inst.dst[1].field == OperandField::ScalarGPR) {
|
||||
const IR::ScalarReg dst_reg{inst.dst[1].code};
|
||||
return ir.SetScalarReg(dst_reg, IR::U32{ir.Select(result, ir.Imm32(1U), ir.Imm32(0U))});
|
||||
}
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
void Translator::V_CNDMASK_B32(const GcnInst& inst) {
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
const IR::ScalarReg flag_reg{inst.src[2].code};
|
||||
const IR::U1 flag = inst.src[2].field == OperandField::ScalarGPR
|
||||
? ir.INotEqual(ir.GetScalarReg(flag_reg), ir.Imm32(0U))
|
||||
: ir.GetVcc();
|
||||
|
||||
// We can treat the instruction as integer most of the time, but when a source is
|
||||
// a floating point constant we will force the other as float for better readability
|
||||
// The other operand is also higly likely to be float as well.
|
||||
const auto is_float_const = [](OperandField field) {
|
||||
return field >= OperandField::ConstFloatPos_0_5 && field <= OperandField::ConstFloatNeg_4_0;
|
||||
};
|
||||
const bool has_flt_source =
|
||||
is_float_const(inst.src[0].field) || is_float_const(inst.src[1].field);
|
||||
const IR::U32F32 src0 = GetSrc(inst.src[0], has_flt_source);
|
||||
const IR::U32F32 src1 = GetSrc(inst.src[1], has_flt_source);
|
||||
const IR::Value result = ir.Select(flag, src1, src0);
|
||||
ir.SetVectorReg(dst_reg, IR::U32F32{result});
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
|
@ -0,0 +1,14 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
void Translator::V_INTERP_P2_F32(const GcnInst& inst) {
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
const IR::Attribute attrib{IR::Attribute::Param0 + inst.control.vintrp.attr};
|
||||
ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
103
src/shader_recompiler/frontend/translate/vector_memory.cpp
Normal file
103
src/shader_recompiler/frontend/translate/vector_memory.cpp
Normal file
|
@ -0,0 +1,103 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
void Translator::IMAGE_GET_RESINFO(const GcnInst& inst) {
|
||||
IR::VectorReg dst_reg{inst.src[1].code};
|
||||
const IR::ScalarReg tsharp_reg{inst.src[2].code};
|
||||
const auto flags = ImageResFlags(inst.control.mimg.dmask);
|
||||
const IR::U32 lod = ir.GetVectorReg(IR::VectorReg(inst.src[0].code));
|
||||
const IR::Value tsharp =
|
||||
ir.CompositeConstruct(ir.GetScalarReg(tsharp_reg), ir.GetScalarReg(tsharp_reg + 1),
|
||||
ir.GetScalarReg(tsharp_reg + 2), ir.GetScalarReg(tsharp_reg + 3));
|
||||
const IR::Value size = ir.ImageQueryDimension(tsharp, lod, ir.Imm1(false));
|
||||
|
||||
if (flags.test(ImageResComponent::Width)) {
|
||||
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 0)});
|
||||
}
|
||||
if (flags.test(ImageResComponent::Height)) {
|
||||
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 1)});
|
||||
}
|
||||
if (flags.test(ImageResComponent::Depth)) {
|
||||
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 2)});
|
||||
}
|
||||
if (flags.test(ImageResComponent::MipCount)) {
|
||||
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 3)});
|
||||
}
|
||||
}
|
||||
|
||||
void Translator::IMAGE_SAMPLE(const GcnInst& inst) {
|
||||
const auto& mimg = inst.control.mimg;
|
||||
ASSERT(!mimg.da);
|
||||
|
||||
IR::VectorReg addr_reg{inst.src[0].code};
|
||||
IR::VectorReg dest_reg{inst.dst[0].code};
|
||||
const IR::ScalarReg tsharp_reg{inst.src[2].code * 4};
|
||||
const IR::ScalarReg sampler_reg{inst.src[3].code * 4};
|
||||
const auto flags = MimgModifierFlags(mimg.mod);
|
||||
|
||||
// Load first dword of T# and S#. We will use them as the handle that will guide resource
|
||||
// tracking pass where to read the sharps. This will later also get patched to the SPIRV texture
|
||||
// binding index.
|
||||
const IR::Value handle =
|
||||
ir.CompositeConstruct(ir.GetScalarReg(tsharp_reg), ir.GetScalarReg(sampler_reg));
|
||||
|
||||
// Load first address components as denoted in 8.2.4 VGPR Usage Sea Islands Series Instruction
|
||||
// Set Architecture
|
||||
const IR::Value offset =
|
||||
flags.test(MimgModifier::Offset) ? ir.GetVectorReg(addr_reg++) : IR::Value{};
|
||||
const IR::F32 bias =
|
||||
flags.test(MimgModifier::LodBias) ? ir.GetVectorReg<IR::F32>(addr_reg++) : IR::F32{};
|
||||
const IR::F32 dref =
|
||||
flags.test(MimgModifier::Pcf) ? ir.GetVectorReg<IR::F32>(addr_reg++) : IR::F32{};
|
||||
|
||||
// Derivatives are tricky because their number depends on the texture type which is located in
|
||||
// T#. We don't have access to T# though until resource tracking pass. For now assume no
|
||||
// derivatives are present, otherwise we don't know where coordinates are placed in the address
|
||||
// stream.
|
||||
ASSERT_MSG(!flags.test(MimgModifier::Derivative), "Derivative image instruction");
|
||||
|
||||
// Now we can load body components as noted in Table 8.9 Image Opcodes with Sampler
|
||||
// Since these are at most 4 dwords, we load them into a single uvec4 and place them
|
||||
// in coords field of the instruction. Then the resource tracking pass will patch the
|
||||
// IR instruction to fill in lod_clamp field. The vector can also be used
|
||||
// as coords directly as SPIR-V will ignore any extra parameters.
|
||||
const IR::Value body =
|
||||
ir.CompositeConstruct(ir.GetVectorReg(addr_reg++), ir.GetVectorReg(addr_reg++),
|
||||
ir.GetVectorReg(addr_reg++), ir.GetVectorReg(addr_reg++));
|
||||
|
||||
// Issue IR instruction, leaving unknown fields blank to patch later.
|
||||
const IR::Value texel = [&]() -> IR::Value {
|
||||
const IR::F32 lod = flags.test(MimgModifier::Level0) ? ir.Imm32(0.f) : IR::F32{};
|
||||
const bool explicit_lod = flags.any(MimgModifier::Level0, MimgModifier::Lod);
|
||||
if (!flags.test(MimgModifier::Pcf)) {
|
||||
if (explicit_lod) {
|
||||
return ir.ImageSampleExplicitLod(handle, body, lod, offset, {});
|
||||
} else {
|
||||
return ir.ImageSampleImplicitLod(handle, body, bias, offset, {}, {});
|
||||
}
|
||||
}
|
||||
if (explicit_lod) {
|
||||
return ir.ImageSampleDrefExplicitLod(handle, body, dref, lod, offset, {});
|
||||
}
|
||||
return ir.ImageSampleDrefImplicitLod(handle, body, dref, bias, offset, {}, {});
|
||||
}();
|
||||
|
||||
for (u32 i = 0; i < 4; i++) {
|
||||
if (((mimg.dmask >> i) & 1) == 0) {
|
||||
continue;
|
||||
}
|
||||
IR::F32 value;
|
||||
if (flags.test(MimgModifier::Pcf)) {
|
||||
value = i < 3 ? IR::F32{texel} : ir.Imm32(1.0f);
|
||||
} else {
|
||||
value = IR::F32{ir.CompositeExtract(texel, i)};
|
||||
}
|
||||
ir.SetVectorReg(dest_reg++, value);
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
Loading…
Add table
Add a link
Reference in a new issue