mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-17 17:05:02 +00:00
video: Import new shader recompiler + display a triangle (#142)
This commit is contained in:
TheTurtle
GitHub
parent
8cf64a33b2
commit
8730968385
103 changed files with 17793 additions and 729 deletions
44
src/shader_recompiler/frontend/translate/data_share.cpp
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44
src/shader_recompiler/frontend/translate/data_share.cpp
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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namespace Shader::Gcn {
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void Translator::DS_READ(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst) {
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const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
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const IR::VectorReg dst_reg{inst.dst[0].code};
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if (is_pair) {
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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ir.SetVectorReg(dst_reg, ir.ReadShared(32, is_signed, addr0));
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1)));
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ir.SetVectorReg(dst_reg + 1, ir.ReadShared(32, is_signed, addr1));
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} else if (bit_size == 64) {
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const IR::Value data = ir.UnpackUint2x32(ir.ReadShared(bit_size, is_signed, addr));
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ir.SetVectorReg(dst_reg, IR::U32{ir.CompositeExtract(data, 0)});
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ir.SetVectorReg(dst_reg + 1, IR::U32{ir.CompositeExtract(data, 1)});
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} else {
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const IR::U32 data = ir.ReadShared(bit_size, is_signed, addr);
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ir.SetVectorReg(dst_reg, data);
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}
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}
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void Translator::DS_WRITE(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst) {
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const IR::U32 addr{ir.GetVectorReg(IR::VectorReg(inst.src[0].code))};
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const IR::VectorReg data0{inst.src[1].code};
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const IR::VectorReg data1{inst.src[2].code};
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if (is_pair) {
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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ir.WriteShared(32, ir.GetVectorReg(data0), addr0);
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1)));
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ir.WriteShared(32, ir.GetVectorReg(data1), addr1);
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} else if (bit_size == 64) {
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const IR::U64 data = ir.PackUint2x32(
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ir.CompositeConstruct(ir.GetVectorReg(data0), ir.GetVectorReg(data0 + 1)));
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ir.WriteShared(bit_size, data, addr);
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} else {
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ir.WriteShared(bit_size, ir.GetVectorReg(data0), addr);
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}
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}
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} // namespace Shader::Gcn
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49
src/shader_recompiler/frontend/translate/export.cpp
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49
src/shader_recompiler/frontend/translate/export.cpp
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@ -0,0 +1,49 @@
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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namespace Shader::Gcn {
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void Translator::EXP(const GcnInst& inst) {
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const auto& exp = inst.control.exp;
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const IR::Attribute attrib{exp.target};
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const std::array vsrc = {
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IR::VectorReg(inst.src[0].code),
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IR::VectorReg(inst.src[1].code),
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IR::VectorReg(inst.src[2].code),
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IR::VectorReg(inst.src[3].code),
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};
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const auto unpack = [&](u32 idx) {
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const IR::Value value = ir.UnpackHalf2x16(ir.GetVectorReg(vsrc[idx]));
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const IR::F32 r = IR::F32{ir.CompositeExtract(value, 0)};
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const IR::F32 g = IR::F32{ir.CompositeExtract(value, 1)};
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ir.SetAttribute(attrib, r, idx * 2);
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ir.SetAttribute(attrib, g, idx * 2 + 1);
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};
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// Components are float16 packed into a VGPR
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if (exp.compr) {
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// Export R, G
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if (exp.en & 1) {
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unpack(0);
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}
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// Export B, A
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if ((exp.en >> 2) & 1) {
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unpack(1);
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}
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} else {
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// Components are float32 into separate VGPRS
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u32 mask = exp.en;
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for (u32 i = 0; i < 4; i++, mask >>= 1) {
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if ((mask & 1) == 0) {
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continue;
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}
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const IR::F32 comp = ir.GetVectorReg<IR::F32>(vsrc[i]);
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ir.SetAttribute(attrib, comp, i);
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}
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}
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}
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} // namespace Shader::Gcn
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0
src/shader_recompiler/frontend/translate/flat_memory.cpp
Normal file
0
src/shader_recompiler/frontend/translate/flat_memory.cpp
Normal file
38
src/shader_recompiler/frontend/translate/scalar_alu.cpp
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38
src/shader_recompiler/frontend/translate/scalar_alu.cpp
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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namespace Shader::Gcn {
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void Translator::S_MOV(const GcnInst& inst) {
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SetDst(inst.dst[0], GetSrc(inst.src[0]));
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}
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void Translator::S_MUL_I32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.IMul(GetSrc(inst.src[0]), GetSrc(inst.src[1])));
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}
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void Translator::S_CMP(ConditionOp cond, bool is_signed, const GcnInst& inst) {
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const IR::U32 lhs = GetSrc(inst.src[0]);
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const IR::U32 rhs = GetSrc(inst.src[1]);
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const IR::U1 result = [&] {
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switch (cond) {
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case ConditionOp::EQ:
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return ir.IEqual(lhs, rhs);
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case ConditionOp::LG:
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return ir.INotEqual(lhs, rhs);
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case ConditionOp::GT:
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return ir.IGreaterThan(lhs, rhs, is_signed);
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case ConditionOp::GE:
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return ir.IGreaterThanEqual(lhs, rhs, is_signed);
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case ConditionOp::LT:
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return ir.ILessThan(lhs, rhs, is_signed);
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case ConditionOp::LE:
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return ir.ILessThanEqual(lhs, rhs, is_signed);
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}
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}();
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// ir.SetScc(result);
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}
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} // namespace Shader::Gcn
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45
src/shader_recompiler/frontend/translate/scalar_memory.cpp
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45
src/shader_recompiler/frontend/translate/scalar_memory.cpp
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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namespace Shader::Gcn {
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void Load(IR::IREmitter& ir, int num_dwords, const IR::Value& handle, IR::ScalarReg dst_reg,
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const IR::U32U64& address) {
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for (u32 i = 0; i < num_dwords; i++) {
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const IR::U32 value = handle.IsEmpty() ? ir.ReadConst(address, ir.Imm32(i))
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: ir.ReadConstBuffer(handle, address, ir.Imm32(i));
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ir.SetScalarReg(dst_reg++, value);
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}
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}
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void Translator::S_LOAD_DWORD(int num_dwords, const GcnInst& inst) {
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const auto& smrd = inst.control.smrd;
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const IR::ScalarReg sbase = IR::ScalarReg(inst.src[0].code * 2);
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const IR::U32 offset =
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smrd.imm ? ir.Imm32(smrd.offset * 4)
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: IR::U32{ir.ShiftLeftLogical(ir.GetScalarReg(IR::ScalarReg(smrd.offset)),
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ir.Imm32(2))};
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const IR::U64 base =
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ir.PackUint2x32(ir.CompositeConstruct(ir.GetScalarReg(sbase), ir.GetScalarReg(sbase + 1)));
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const IR::U64 address = ir.IAdd(base, offset);
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const IR::ScalarReg dst_reg{inst.dst[0].code};
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Load(ir, num_dwords, {}, dst_reg, address);
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}
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void Translator::S_BUFFER_LOAD_DWORD(int num_dwords, const GcnInst& inst) {
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const auto& smrd = inst.control.smrd;
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const IR::ScalarReg sbase = IR::ScalarReg(inst.src[0].code * 2);
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const IR::U32 offset =
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smrd.imm ? ir.Imm32(smrd.offset * 4)
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: IR::U32{ir.ShiftLeftLogical(ir.GetScalarReg(IR::ScalarReg(smrd.offset)),
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ir.Imm32(2))};
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const IR::Value vsharp =
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ir.CompositeConstruct(ir.GetScalarReg(sbase), ir.GetScalarReg(sbase + 1),
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ir.GetScalarReg(sbase + 2), ir.GetScalarReg(sbase + 3));
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const IR::ScalarReg dst_reg{inst.dst[0].code};
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Load(ir, num_dwords, vsharp, dst_reg, offset);
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}
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} // namespace Shader::Gcn
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152
src/shader_recompiler/frontend/translate/translate.cpp
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152
src/shader_recompiler/frontend/translate/translate.cpp
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Gcn {
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Translator::Translator(IR::Block* block_, Stage stage) : block{block_}, ir{*block} {
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IR::VectorReg dst_vreg = IR::VectorReg::V0;
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switch (stage) {
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case Stage::Vertex:
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// https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L146C1-L146C23
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::PrimitiveId));
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break;
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case Stage::Fragment:
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// https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L258
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// The first two VGPRs are used for i/j barycentric coordinates. In the vast majority of
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// cases it will be only those two, but if shader is using both e.g linear and perspective
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// inputs it can be more For now assume that this isn't the case.
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dst_vreg = IR::VectorReg::V2;
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for (u32 i = 0; i < 4; i++) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttribute(IR::Attribute::FragCoord, i));
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}
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::IsFrontFace));
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break;
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default:
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throw NotImplementedException("Unknown shader stage");
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}
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// Initialize user data.
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IR::ScalarReg dst_sreg = IR::ScalarReg::S0;
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for (u32 i = 0; i < 16; i++) {
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ir.SetScalarReg(dst_sreg++, ir.Imm32(0U));
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}
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}
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IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (operand.type == ScalarType::Float32 || force_flt) {
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return ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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} else {
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return ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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}
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case OperandField::VectorGPR:
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if (operand.type == ScalarType::Float32 || force_flt) {
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return ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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} else {
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return ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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}
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case OperandField::ConstZero:
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if (force_flt) {
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return ir.Imm32(0.f);
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} else {
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return ir.Imm32(0U);
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}
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case OperandField::SignedConstIntPos:
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ASSERT(!force_flt);
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return ir.Imm32(operand.code - SignedConstIntPosMin + 1);
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case OperandField::SignedConstIntNeg:
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ASSERT(!force_flt);
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return ir.Imm32(-s32(operand.code) + SignedConstIntNegMin - 1);
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case OperandField::LiteralConst:
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ASSERT(!force_flt);
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return ir.Imm32(operand.code);
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case OperandField::ConstFloatPos_1_0:
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return ir.Imm32(1.f);
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case OperandField::ConstFloatPos_0_5:
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return ir.Imm32(0.5f);
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case OperandField::ConstFloatNeg_0_5:
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return ir.Imm32(-0.5f);
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default:
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UNREACHABLE();
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}
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}
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void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
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switch (operand.field) {
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case OperandField::ScalarGPR:
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return ir.SetScalarReg(IR::ScalarReg(operand.code), value);
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case OperandField::VectorGPR:
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return ir.SetVectorReg(IR::VectorReg(operand.code), value);
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case OperandField::VccHi:
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case OperandField::M0:
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break; // Ignore for now
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default:
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UNREACHABLE();
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}
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}
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void Translate(IR::Block* block, Stage stage, std::span<const GcnInst> inst_list) {
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if (inst_list.empty()) {
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return;
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}
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Translator translator{block, stage};
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for (const auto& inst : inst_list) {
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switch (inst.opcode) {
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case Opcode::S_MOV_B32:
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translator.S_MOV(inst);
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break;
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case Opcode::S_MUL_I32:
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translator.S_MUL_I32(inst);
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break;
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case Opcode::V_MOV_B32:
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translator.V_MOV(inst);
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break;
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case Opcode::V_MAC_F32:
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translator.V_MAC_F32(inst);
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break;
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case Opcode::V_MUL_F32:
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translator.V_MUL_F32(inst);
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break;
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case Opcode::S_SWAPPC_B64:
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case Opcode::S_WAITCNT:
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break; // Ignore for now.
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case Opcode::S_BUFFER_LOAD_DWORDX16:
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translator.S_BUFFER_LOAD_DWORD(16, inst);
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break;
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case Opcode::EXP:
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translator.EXP(inst);
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break;
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case Opcode::V_INTERP_P2_F32:
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translator.V_INTERP_P2_F32(inst);
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break;
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case Opcode::V_CVT_PKRTZ_F16_F32:
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translator.V_CVT_PKRTZ_F16_F32(inst);
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break;
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case Opcode::IMAGE_SAMPLE:
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translator.IMAGE_SAMPLE(inst);
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break;
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case Opcode::V_CMP_EQ_U32:
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translator.V_CMP_EQ_U32(inst);
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break;
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case Opcode::V_CNDMASK_B32:
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translator.V_CNDMASK_B32(inst);
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break;
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case Opcode::S_MOV_B64:
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case Opcode::S_WQM_B64:
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case Opcode::V_INTERP_P1_F32:
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case Opcode::S_ENDPGM:
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break;
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default:
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UNREACHABLE_MSG("Unknown opcode {}", u32(inst.opcode));
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}
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}
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}
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} // namespace Shader::Gcn
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73
src/shader_recompiler/frontend/translate/translate.h
Normal file
73
src/shader_recompiler/frontend/translate/translate.h
Normal file
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <span>
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#include "shader_recompiler/frontend/instruction.h"
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#include "shader_recompiler/ir/basic_block.h"
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#include "shader_recompiler/ir/ir_emitter.h"
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namespace Shader {
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enum class Stage : u32;
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}
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namespace Shader::Gcn {
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enum class ConditionOp : u32 {
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EQ,
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LG,
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GT,
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GE,
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LT,
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LE,
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};
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class Translator {
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public:
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explicit Translator(IR::Block* block_, Stage stage);
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// Scalar ALU
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void S_MOV(const GcnInst& inst);
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void S_MUL_I32(const GcnInst& inst);
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void S_CMP(ConditionOp cond, bool is_signed, const GcnInst& inst);
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// Scalar Memory
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void S_LOAD_DWORD(int num_dwords, const GcnInst& inst);
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void S_BUFFER_LOAD_DWORD(int num_dwords, const GcnInst& inst);
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// Vector ALU
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void V_MOV(const GcnInst& inst);
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void V_SAD(const GcnInst& inst);
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void V_MAC_F32(const GcnInst& inst);
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void V_CVT_PKRTZ_F16_F32(const GcnInst& inst);
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void V_MUL_F32(const GcnInst& inst);
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void V_CMP_EQ_U32(const GcnInst& inst);
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void V_CNDMASK_B32(const GcnInst& inst);
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// Vector interpolation
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void V_INTERP_P2_F32(const GcnInst& inst);
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// Data share
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void DS_READ(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst);
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void DS_WRITE(int bit_size, bool is_signed, bool is_pair, const GcnInst& inst);
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// MIMG
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void IMAGE_GET_RESINFO(const GcnInst& inst);
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||||
void IMAGE_SAMPLE(const GcnInst& inst);
|
||||
|
||||
// Export
|
||||
void EXP(const GcnInst& inst);
|
||||
|
||||
private:
|
||||
IR::U32F32 GetSrc(const InstOperand& operand, bool flt_zero = false);
|
||||
void SetDst(const InstOperand& operand, const IR::U32F32& value);
|
||||
|
||||
private:
|
||||
IR::Block* block;
|
||||
IR::IREmitter ir;
|
||||
};
|
||||
|
||||
void Translate(IR::Block* block, Stage stage, std::span<const GcnInst> inst_list);
|
||||
|
||||
} // namespace Shader::Gcn
|
||||
65
src/shader_recompiler/frontend/translate/vector_alu.cpp
Normal file
65
src/shader_recompiler/frontend/translate/vector_alu.cpp
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
#pragma clang optimize off
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
void Translator::V_MOV(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], GetSrc(inst.src[0]));
|
||||
}
|
||||
|
||||
void Translator::V_SAD(const GcnInst& inst) {
|
||||
const IR::U32 abs_diff = ir.IAbs(ir.ISub(GetSrc(inst.src[0]), GetSrc(inst.src[1])));
|
||||
SetDst(inst.dst[0], ir.IAdd(abs_diff, GetSrc(inst.src[2])));
|
||||
}
|
||||
|
||||
void Translator::V_MAC_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], ir.FPFma(GetSrc(inst.src[0]), GetSrc(inst.src[1]), GetSrc(inst.dst[0])));
|
||||
}
|
||||
|
||||
void Translator::V_CVT_PKRTZ_F16_F32(const GcnInst& inst) {
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
const IR::Value vec_f32 = ir.CompositeConstruct(ir.FPConvert(16, GetSrc(inst.src[0])),
|
||||
ir.FPConvert(16, GetSrc(inst.src[1])));
|
||||
ir.SetVectorReg(dst_reg, ir.PackFloat2x16(vec_f32));
|
||||
}
|
||||
|
||||
void Translator::V_MUL_F32(const GcnInst& inst) {
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
ir.SetVectorReg(dst_reg, ir.FPMul(GetSrc(inst.src[0]), GetSrc(inst.src[1])));
|
||||
}
|
||||
|
||||
void Translator::V_CMP_EQ_U32(const GcnInst& inst) {
|
||||
const IR::U1 result = ir.IEqual(GetSrc(inst.src[0]), GetSrc(inst.src[1]));
|
||||
if (inst.dst[1].field == OperandField::VccLo) {
|
||||
return ir.SetVcc(result);
|
||||
} else if (inst.dst[1].field == OperandField::ScalarGPR) {
|
||||
const IR::ScalarReg dst_reg{inst.dst[1].code};
|
||||
return ir.SetScalarReg(dst_reg, IR::U32{ir.Select(result, ir.Imm32(1U), ir.Imm32(0U))});
|
||||
}
|
||||
UNREACHABLE();
|
||||
}
|
||||
|
||||
void Translator::V_CNDMASK_B32(const GcnInst& inst) {
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
const IR::ScalarReg flag_reg{inst.src[2].code};
|
||||
const IR::U1 flag = inst.src[2].field == OperandField::ScalarGPR
|
||||
? ir.INotEqual(ir.GetScalarReg(flag_reg), ir.Imm32(0U))
|
||||
: ir.GetVcc();
|
||||
|
||||
// We can treat the instruction as integer most of the time, but when a source is
|
||||
// a floating point constant we will force the other as float for better readability
|
||||
// The other operand is also higly likely to be float as well.
|
||||
const auto is_float_const = [](OperandField field) {
|
||||
return field >= OperandField::ConstFloatPos_0_5 && field <= OperandField::ConstFloatNeg_4_0;
|
||||
};
|
||||
const bool has_flt_source =
|
||||
is_float_const(inst.src[0].field) || is_float_const(inst.src[1].field);
|
||||
const IR::U32F32 src0 = GetSrc(inst.src[0], has_flt_source);
|
||||
const IR::U32F32 src1 = GetSrc(inst.src[1], has_flt_source);
|
||||
const IR::Value result = ir.Select(flag, src1, src0);
|
||||
ir.SetVectorReg(dst_reg, IR::U32F32{result});
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
void Translator::V_INTERP_P2_F32(const GcnInst& inst) {
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
const IR::Attribute attrib{IR::Attribute::Param0 + inst.control.vintrp.attr};
|
||||
ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
||||
103
src/shader_recompiler/frontend/translate/vector_memory.cpp
Normal file
103
src/shader_recompiler/frontend/translate/vector_memory.cpp
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#include "shader_recompiler/frontend/translate/translate.h"
|
||||
|
||||
namespace Shader::Gcn {
|
||||
|
||||
void Translator::IMAGE_GET_RESINFO(const GcnInst& inst) {
|
||||
IR::VectorReg dst_reg{inst.src[1].code};
|
||||
const IR::ScalarReg tsharp_reg{inst.src[2].code};
|
||||
const auto flags = ImageResFlags(inst.control.mimg.dmask);
|
||||
const IR::U32 lod = ir.GetVectorReg(IR::VectorReg(inst.src[0].code));
|
||||
const IR::Value tsharp =
|
||||
ir.CompositeConstruct(ir.GetScalarReg(tsharp_reg), ir.GetScalarReg(tsharp_reg + 1),
|
||||
ir.GetScalarReg(tsharp_reg + 2), ir.GetScalarReg(tsharp_reg + 3));
|
||||
const IR::Value size = ir.ImageQueryDimension(tsharp, lod, ir.Imm1(false));
|
||||
|
||||
if (flags.test(ImageResComponent::Width)) {
|
||||
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 0)});
|
||||
}
|
||||
if (flags.test(ImageResComponent::Height)) {
|
||||
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 1)});
|
||||
}
|
||||
if (flags.test(ImageResComponent::Depth)) {
|
||||
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 2)});
|
||||
}
|
||||
if (flags.test(ImageResComponent::MipCount)) {
|
||||
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 3)});
|
||||
}
|
||||
}
|
||||
|
||||
void Translator::IMAGE_SAMPLE(const GcnInst& inst) {
|
||||
const auto& mimg = inst.control.mimg;
|
||||
ASSERT(!mimg.da);
|
||||
|
||||
IR::VectorReg addr_reg{inst.src[0].code};
|
||||
IR::VectorReg dest_reg{inst.dst[0].code};
|
||||
const IR::ScalarReg tsharp_reg{inst.src[2].code * 4};
|
||||
const IR::ScalarReg sampler_reg{inst.src[3].code * 4};
|
||||
const auto flags = MimgModifierFlags(mimg.mod);
|
||||
|
||||
// Load first dword of T# and S#. We will use them as the handle that will guide resource
|
||||
// tracking pass where to read the sharps. This will later also get patched to the SPIRV texture
|
||||
// binding index.
|
||||
const IR::Value handle =
|
||||
ir.CompositeConstruct(ir.GetScalarReg(tsharp_reg), ir.GetScalarReg(sampler_reg));
|
||||
|
||||
// Load first address components as denoted in 8.2.4 VGPR Usage Sea Islands Series Instruction
|
||||
// Set Architecture
|
||||
const IR::Value offset =
|
||||
flags.test(MimgModifier::Offset) ? ir.GetVectorReg(addr_reg++) : IR::Value{};
|
||||
const IR::F32 bias =
|
||||
flags.test(MimgModifier::LodBias) ? ir.GetVectorReg<IR::F32>(addr_reg++) : IR::F32{};
|
||||
const IR::F32 dref =
|
||||
flags.test(MimgModifier::Pcf) ? ir.GetVectorReg<IR::F32>(addr_reg++) : IR::F32{};
|
||||
|
||||
// Derivatives are tricky because their number depends on the texture type which is located in
|
||||
// T#. We don't have access to T# though until resource tracking pass. For now assume no
|
||||
// derivatives are present, otherwise we don't know where coordinates are placed in the address
|
||||
// stream.
|
||||
ASSERT_MSG(!flags.test(MimgModifier::Derivative), "Derivative image instruction");
|
||||
|
||||
// Now we can load body components as noted in Table 8.9 Image Opcodes with Sampler
|
||||
// Since these are at most 4 dwords, we load them into a single uvec4 and place them
|
||||
// in coords field of the instruction. Then the resource tracking pass will patch the
|
||||
// IR instruction to fill in lod_clamp field. The vector can also be used
|
||||
// as coords directly as SPIR-V will ignore any extra parameters.
|
||||
const IR::Value body =
|
||||
ir.CompositeConstruct(ir.GetVectorReg(addr_reg++), ir.GetVectorReg(addr_reg++),
|
||||
ir.GetVectorReg(addr_reg++), ir.GetVectorReg(addr_reg++));
|
||||
|
||||
// Issue IR instruction, leaving unknown fields blank to patch later.
|
||||
const IR::Value texel = [&]() -> IR::Value {
|
||||
const IR::F32 lod = flags.test(MimgModifier::Level0) ? ir.Imm32(0.f) : IR::F32{};
|
||||
const bool explicit_lod = flags.any(MimgModifier::Level0, MimgModifier::Lod);
|
||||
if (!flags.test(MimgModifier::Pcf)) {
|
||||
if (explicit_lod) {
|
||||
return ir.ImageSampleExplicitLod(handle, body, lod, offset, {});
|
||||
} else {
|
||||
return ir.ImageSampleImplicitLod(handle, body, bias, offset, {}, {});
|
||||
}
|
||||
}
|
||||
if (explicit_lod) {
|
||||
return ir.ImageSampleDrefExplicitLod(handle, body, dref, lod, offset, {});
|
||||
}
|
||||
return ir.ImageSampleDrefImplicitLod(handle, body, dref, bias, offset, {}, {});
|
||||
}();
|
||||
|
||||
for (u32 i = 0; i < 4; i++) {
|
||||
if (((mimg.dmask >> i) & 1) == 0) {
|
||||
continue;
|
||||
}
|
||||
IR::F32 value;
|
||||
if (flags.test(MimgModifier::Pcf)) {
|
||||
value = i < 3 ? IR::F32{texel} : ir.Imm32(1.0f);
|
||||
} else {
|
||||
value = IR::F32{ir.CompositeExtract(texel, i)};
|
||||
}
|
||||
ir.SetVectorReg(dest_reg++, value);
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Shader::Gcn
|
||||
Loading…
Add table
Add a link
Reference in a new issue