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video: Import new shader recompiler + display a triangle (#142)
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TheTurtle
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commit
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103 changed files with 17793 additions and 729 deletions
152
src/shader_recompiler/frontend/translate/translate.cpp
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152
src/shader_recompiler/frontend/translate/translate.cpp
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/translate/translate.h"
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#include "shader_recompiler/runtime_info.h"
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namespace Shader::Gcn {
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Translator::Translator(IR::Block* block_, Stage stage) : block{block_}, ir{*block} {
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IR::VectorReg dst_vreg = IR::VectorReg::V0;
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switch (stage) {
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case Stage::Vertex:
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// https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L146C1-L146C23
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::PrimitiveId));
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break;
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case Stage::Fragment:
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// https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L258
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// The first two VGPRs are used for i/j barycentric coordinates. In the vast majority of
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// cases it will be only those two, but if shader is using both e.g linear and perspective
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// inputs it can be more For now assume that this isn't the case.
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dst_vreg = IR::VectorReg::V2;
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for (u32 i = 0; i < 4; i++) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttribute(IR::Attribute::FragCoord, i));
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}
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::IsFrontFace));
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break;
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default:
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throw NotImplementedException("Unknown shader stage");
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}
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// Initialize user data.
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IR::ScalarReg dst_sreg = IR::ScalarReg::S0;
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for (u32 i = 0; i < 16; i++) {
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ir.SetScalarReg(dst_sreg++, ir.Imm32(0U));
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}
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}
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IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool force_flt) {
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (operand.type == ScalarType::Float32 || force_flt) {
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return ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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} else {
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return ir.GetScalarReg<IR::U32>(IR::ScalarReg(operand.code));
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}
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case OperandField::VectorGPR:
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if (operand.type == ScalarType::Float32 || force_flt) {
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return ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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} else {
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return ir.GetVectorReg<IR::U32>(IR::VectorReg(operand.code));
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}
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case OperandField::ConstZero:
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if (force_flt) {
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return ir.Imm32(0.f);
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} else {
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return ir.Imm32(0U);
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}
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case OperandField::SignedConstIntPos:
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ASSERT(!force_flt);
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return ir.Imm32(operand.code - SignedConstIntPosMin + 1);
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case OperandField::SignedConstIntNeg:
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ASSERT(!force_flt);
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return ir.Imm32(-s32(operand.code) + SignedConstIntNegMin - 1);
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case OperandField::LiteralConst:
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ASSERT(!force_flt);
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return ir.Imm32(operand.code);
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case OperandField::ConstFloatPos_1_0:
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return ir.Imm32(1.f);
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case OperandField::ConstFloatPos_0_5:
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return ir.Imm32(0.5f);
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case OperandField::ConstFloatNeg_0_5:
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return ir.Imm32(-0.5f);
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default:
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UNREACHABLE();
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}
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}
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void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
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switch (operand.field) {
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case OperandField::ScalarGPR:
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return ir.SetScalarReg(IR::ScalarReg(operand.code), value);
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case OperandField::VectorGPR:
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return ir.SetVectorReg(IR::VectorReg(operand.code), value);
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case OperandField::VccHi:
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case OperandField::M0:
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break; // Ignore for now
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default:
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UNREACHABLE();
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}
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}
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void Translate(IR::Block* block, Stage stage, std::span<const GcnInst> inst_list) {
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if (inst_list.empty()) {
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return;
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}
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Translator translator{block, stage};
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for (const auto& inst : inst_list) {
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switch (inst.opcode) {
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case Opcode::S_MOV_B32:
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translator.S_MOV(inst);
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break;
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case Opcode::S_MUL_I32:
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translator.S_MUL_I32(inst);
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break;
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case Opcode::V_MOV_B32:
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translator.V_MOV(inst);
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break;
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case Opcode::V_MAC_F32:
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translator.V_MAC_F32(inst);
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break;
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case Opcode::V_MUL_F32:
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translator.V_MUL_F32(inst);
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break;
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case Opcode::S_SWAPPC_B64:
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case Opcode::S_WAITCNT:
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break; // Ignore for now.
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case Opcode::S_BUFFER_LOAD_DWORDX16:
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translator.S_BUFFER_LOAD_DWORD(16, inst);
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break;
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case Opcode::EXP:
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translator.EXP(inst);
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break;
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case Opcode::V_INTERP_P2_F32:
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translator.V_INTERP_P2_F32(inst);
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break;
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case Opcode::V_CVT_PKRTZ_F16_F32:
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translator.V_CVT_PKRTZ_F16_F32(inst);
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break;
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case Opcode::IMAGE_SAMPLE:
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translator.IMAGE_SAMPLE(inst);
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break;
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case Opcode::V_CMP_EQ_U32:
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translator.V_CMP_EQ_U32(inst);
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break;
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case Opcode::V_CNDMASK_B32:
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translator.V_CNDMASK_B32(inst);
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break;
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case Opcode::S_MOV_B64:
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case Opcode::S_WQM_B64:
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case Opcode::V_INTERP_P1_F32:
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case Opcode::S_ENDPGM:
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break;
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default:
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UNREACHABLE_MSG("Unknown opcode {}", u32(inst.opcode));
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}
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}
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}
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} // namespace Shader::Gcn
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