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ir_passes: Fold readlane with ff1 pattern (#3224)

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TheTurtle 2025-07-10 14:19:44 +03:00 • committed by GitHub
parent ee97c5c110
commit 88abb93669
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3 changed files with 17 additions and 4 deletions
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2
src/shader_recompiler/backend/spirv/emit_spirv_instructions.h
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@ -529,7 +529,7 @@ Id EmitLaneId(EmitContext& ctx);
Id EmitWarpId(EmitContext& ctx);
Id EmitQuadShuffle(EmitContext& ctx, Id value, Id index);
Id EmitReadFirstLane(EmitContext& ctx, Id value);
Id EmitReadLane(EmitContext& ctx, Id value, u32 lane);
Id EmitReadLane(EmitContext& ctx, Id value, Id lane);
Id EmitWriteLane(EmitContext& ctx, Id value, Id write_value, u32 lane);
Id EmitDataAppend(EmitContext& ctx, u32 gds_addr, u32 binding);
Id EmitDataConsume(EmitContext& ctx, u32 gds_addr, u32 binding);

5
src/shader_recompiler/backend/spirv/emit_spirv_warp.cpp
View file

@ -26,9 +26,8 @@ Id EmitReadFirstLane(EmitContext& ctx, Id value) {
return ctx.OpGroupNonUniformBroadcastFirst(ctx.U32[1], SubgroupScope(ctx), value);
}
Id EmitReadLane(EmitContext& ctx, Id value, u32 lane) {
return ctx.OpGroupNonUniformBroadcast(ctx.U32[1], SubgroupScope(ctx), value,
ctx.ConstU32(lane));
Id EmitReadLane(EmitContext& ctx, Id value, Id lane) {
return ctx.OpGroupNonUniformBroadcast(ctx.U32[1], SubgroupScope(ctx), value, lane);
}
Id EmitWriteLane(EmitContext& ctx, Id value, Id write_value, u32 lane) {

14
src/shader_recompiler/ir/passes/readlane_elimination_pass.cpp
View file

@ -95,6 +95,20 @@ void ReadLaneEliminationPass(IR::Program& program) {
if (inst.GetOpcode() != IR::Opcode::ReadLane) {
continue;
}
// Check for the following pattern and replace it with ReadFirstLane
// s_ff1_i32_b64 sgpr, exec
// v_readlane_b32 sdst, vgpr, sgpr
if (const auto lane = inst.Arg(1); !lane.IsImmediate()) {
if (lane.InstRecursive()->GetOpcode() == IR::Opcode::FindILsb64) {
const auto value = inst.Arg(0);
inst.ReplaceOpcode(IR::Opcode::ReadFirstLane);
inst.ClearArgs();
inst.SetArg(0, value);
}
continue;
}
const u32 lane = inst.Arg(1).U32();
IR::Inst* prod = inst.Arg(0).InstRecursive();