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libraries: gnmdriver: few more functions implemented (#1544)

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psucien 2024-11-18 10:23:21 +01:00 • committed by GitHub
parent e1fecda74f
commit 8fbd9187f8
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9 changed files with 119 additions and 17 deletions
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24
src/video_core/amdgpu/liverpool.cpp
View file

@ -417,7 +417,7 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
if (rasterizer) {
const auto cmd_address = reinterpret_cast<const void*>(header);
rasterizer->ScopeMarkerBegin(fmt::format("dcb:{}:DrawIndirect", cmd_address));
rasterizer->DrawIndirect(false, ib_address, offset, size);
rasterizer->DrawIndirect(false, ib_address, offset, size, 1, 0);
rasterizer->ScopeMarkerEnd();
}
break;
@ -435,7 +435,27 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
const auto cmd_address = reinterpret_cast<const void*>(header);
rasterizer->ScopeMarkerBegin(
fmt::format("dcb:{}:DrawIndexIndirect", cmd_address));
rasterizer->DrawIndirect(true, ib_address, offset, size);
rasterizer->DrawIndirect(true, ib_address, offset, size, 1, 0);
rasterizer->ScopeMarkerEnd();
}
break;
}
case PM4ItOpcode::DrawIndexIndirectCountMulti: {
const auto* draw_index_indirect =
reinterpret_cast<const PM4CmdDrawIndexIndirect*>(header);
const auto offset = draw_index_indirect->data_offset;
const auto ib_address = mapped_queues[GfxQueueId].indirect_args_addr;
const auto size = sizeof(PM4CmdDrawIndexIndirect::DrawIndexInstancedArgs);
if (DebugState.DumpingCurrentReg()) {
DebugState.PushRegsDump(base_addr, reinterpret_cast<uintptr_t>(header), regs);
}
if (rasterizer) {
const auto cmd_address = reinterpret_cast<const void*>(header);
rasterizer->ScopeMarkerBegin(
fmt::format("dcb:{}:DrawIndexIndirectCountMulti", cmd_address));
rasterizer->DrawIndirect(true, ib_address, offset, size,
draw_index_indirect->count,
draw_index_indirect->countAddr);
rasterizer->ScopeMarkerEnd();
}
break;

2
src/video_core/amdgpu/liverpool.h
View file

@ -57,6 +57,8 @@ struct Liverpool {
static constexpr u32 ConfigRegWordOffset = 0x2000;
static constexpr u32 ShRegWordOffset = 0x2C00;
static constexpr u32 NumRegs = 0xD000;
static constexpr u32 DrawIndirectArgsSize = 0x10u;
static constexpr u32 DrawIndexedIndirectArgsSize = 0x14u;
using UserData = std::array<u32, NumShaderUserData>;

16
src/video_core/amdgpu/pm4_cmds.h
View file

@ -817,11 +817,25 @@ struct PM4CmdDrawIndexIndirect {
BitField<0, 16, u32> base_vtx_loc; ///< Offset where the CP will write the
///< BaseVertexLocation it fetched from memory
};
union { // NOTE: this one is undocumented in AMD spec, but Gnm driver writes this field
union {
u32 dw3;
BitField<0, 16, u32> start_inst_loc; ///< Offset where the CP will write the
///< StartInstanceLocation it fetched from memory
};
union {
u32 dw4;
struct {
BitField<0, 16, u32> drawIndexLoc; ///< register offset to write the Draw Index count
BitField<30, 1, u32>
countIndirectEnable; ///< Indicates the data structure count is in memory
BitField<31, 1, u32>
drawIndexEnable; ///< Enables writing of Draw Index count to DRAW_INDEX_LOC
};
};
u32 count; ///< Count of data structures to loop through before going to next packet
u64 countAddr; ///< DWord aligned Address[31:2]; Valid if countIndirectEnable is set
u32 stride; ///< Stride in memory from one data structure to the next
u32 draw_initiator; ///< Draw Initiator Register
};

1
src/video_core/amdgpu/pm4_opcodes.h
View file

@ -71,6 +71,7 @@ enum class PM4ItOpcode : u32 {
IncrementDeCounter = 0x85,
WaitOnCeCounter = 0x86,
WaitOnDeCounterDiff = 0x88,
DrawIndexIndirectCountMulti = 0x9d,
};
} // namespace AmdGpu