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https://github.com/shadps4-emu/shadPS4.git
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libraries: gnmdriver: few more functions implemented (#1544)
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parent
e1fecda74f
commit
8fbd9187f8
9 changed files with 119 additions and 17 deletions
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@ -345,6 +345,7 @@ bool Instance::CreateDevice() {
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},
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vk::PhysicalDeviceVulkan12Features{
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.samplerMirrorClampToEdge = vk12_features.samplerMirrorClampToEdge,
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.drawIndirectCount = vk12_features.drawIndirectCount,
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.shaderFloat16 = vk12_features.shaderFloat16,
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.scalarBlockLayout = vk12_features.scalarBlockLayout,
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.uniformBufferStandardLayout = vk12_features.uniformBufferStandardLayout,
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@ -115,14 +115,14 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
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}
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}
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void Rasterizer::DrawIndirect(bool is_indexed, VAddr address, u32 offset, u32 size) {
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void Rasterizer::DrawIndirect(bool is_indexed, VAddr arg_address, u32 offset, u32 size,
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u32 max_count, VAddr count_address) {
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RENDERER_TRACE;
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if (!FilterDraw()) {
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return;
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}
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const auto cmdbuf = scheduler.CommandBuffer();
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const auto& regs = liverpool->regs;
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const GraphicsPipeline* pipeline = pipeline_cache.GetGraphicsPipeline();
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if (!pipeline) {
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@ -142,7 +142,13 @@ void Rasterizer::DrawIndirect(bool is_indexed, VAddr address, u32 offset, u32 si
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buffer_cache.BindVertexBuffers(vs_info);
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buffer_cache.BindIndexBuffer(is_indexed, 0);
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const auto [buffer, base] = buffer_cache.ObtainBuffer(address + offset, size, false);
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const auto [buffer, base] = buffer_cache.ObtainBuffer(arg_address + offset, size, false);
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VideoCore::Buffer* count_buffer{};
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u32 count_base{};
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if (count_address != 0) {
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std::tie(count_buffer, count_base) = buffer_cache.ObtainBuffer(count_address, 4, false);
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}
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BeginRendering(*pipeline);
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UpdateDynamicState(*pipeline);
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@ -150,10 +156,29 @@ void Rasterizer::DrawIndirect(bool is_indexed, VAddr address, u32 offset, u32 si
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// We can safely ignore both SGPR UD indices and results of fetch shader parsing, as vertex and
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// instance offsets will be automatically applied by Vulkan from indirect args buffer.
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const auto cmdbuf = scheduler.CommandBuffer();
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if (is_indexed) {
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cmdbuf.drawIndexedIndirect(buffer->Handle(), base, 1, 0);
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static_assert(sizeof(VkDrawIndexedIndirectCommand) ==
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AmdGpu::Liverpool::DrawIndexedIndirectArgsSize);
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if (count_address != 0) {
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cmdbuf.drawIndexedIndirectCount(buffer->Handle(), base, count_buffer->Handle(),
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count_base, max_count,
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AmdGpu::Liverpool::DrawIndexedIndirectArgsSize);
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} else {
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cmdbuf.drawIndexedIndirect(buffer->Handle(), base, max_count,
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AmdGpu::Liverpool::DrawIndexedIndirectArgsSize);
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}
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} else {
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cmdbuf.drawIndirect(buffer->Handle(), base, 1, 0);
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static_assert(sizeof(VkDrawIndirectCommand) == AmdGpu::Liverpool::DrawIndirectArgsSize);
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if (count_address != 0) {
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cmdbuf.drawIndirectCount(buffer->Handle(), base, count_buffer->Handle(), count_base,
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max_count, AmdGpu::Liverpool::DrawIndirectArgsSize);
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} else {
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cmdbuf.drawIndirect(buffer->Handle(), base, max_count,
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AmdGpu::Liverpool::DrawIndirectArgsSize);
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}
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}
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}
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@ -32,7 +32,8 @@ public:
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}
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void Draw(bool is_indexed, u32 index_offset = 0);
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void DrawIndirect(bool is_indexed, VAddr address, u32 offset, u32 size);
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void DrawIndirect(bool is_indexed, VAddr arg_address, u32 offset, u32 size, u32 max_count,
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VAddr count_address);
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void DispatchDirect();
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void DispatchIndirect(VAddr address, u32 offset, u32 size);
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