libraries: gnmdriver: few more functions implemented (#1544)

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psucien 2024-11-18 10:23:21 +01:00 committed by GitHub
parent e1fecda74f
commit 8fbd9187f8
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GPG key ID: B5690EEEBB952194
9 changed files with 119 additions and 17 deletions

View file

@ -345,6 +345,7 @@ bool Instance::CreateDevice() {
},
vk::PhysicalDeviceVulkan12Features{
.samplerMirrorClampToEdge = vk12_features.samplerMirrorClampToEdge,
.drawIndirectCount = vk12_features.drawIndirectCount,
.shaderFloat16 = vk12_features.shaderFloat16,
.scalarBlockLayout = vk12_features.scalarBlockLayout,
.uniformBufferStandardLayout = vk12_features.uniformBufferStandardLayout,

View file

@ -115,14 +115,14 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
}
}
void Rasterizer::DrawIndirect(bool is_indexed, VAddr address, u32 offset, u32 size) {
void Rasterizer::DrawIndirect(bool is_indexed, VAddr arg_address, u32 offset, u32 size,
u32 max_count, VAddr count_address) {
RENDERER_TRACE;
if (!FilterDraw()) {
return;
}
const auto cmdbuf = scheduler.CommandBuffer();
const auto& regs = liverpool->regs;
const GraphicsPipeline* pipeline = pipeline_cache.GetGraphicsPipeline();
if (!pipeline) {
@ -142,7 +142,13 @@ void Rasterizer::DrawIndirect(bool is_indexed, VAddr address, u32 offset, u32 si
buffer_cache.BindVertexBuffers(vs_info);
buffer_cache.BindIndexBuffer(is_indexed, 0);
const auto [buffer, base] = buffer_cache.ObtainBuffer(address + offset, size, false);
const auto [buffer, base] = buffer_cache.ObtainBuffer(arg_address + offset, size, false);
VideoCore::Buffer* count_buffer{};
u32 count_base{};
if (count_address != 0) {
std::tie(count_buffer, count_base) = buffer_cache.ObtainBuffer(count_address, 4, false);
}
BeginRendering(*pipeline);
UpdateDynamicState(*pipeline);
@ -150,10 +156,29 @@ void Rasterizer::DrawIndirect(bool is_indexed, VAddr address, u32 offset, u32 si
// We can safely ignore both SGPR UD indices and results of fetch shader parsing, as vertex and
// instance offsets will be automatically applied by Vulkan from indirect args buffer.
const auto cmdbuf = scheduler.CommandBuffer();
if (is_indexed) {
cmdbuf.drawIndexedIndirect(buffer->Handle(), base, 1, 0);
static_assert(sizeof(VkDrawIndexedIndirectCommand) ==
AmdGpu::Liverpool::DrawIndexedIndirectArgsSize);
if (count_address != 0) {
cmdbuf.drawIndexedIndirectCount(buffer->Handle(), base, count_buffer->Handle(),
count_base, max_count,
AmdGpu::Liverpool::DrawIndexedIndirectArgsSize);
} else {
cmdbuf.drawIndexedIndirect(buffer->Handle(), base, max_count,
AmdGpu::Liverpool::DrawIndexedIndirectArgsSize);
}
} else {
cmdbuf.drawIndirect(buffer->Handle(), base, 1, 0);
static_assert(sizeof(VkDrawIndirectCommand) == AmdGpu::Liverpool::DrawIndirectArgsSize);
if (count_address != 0) {
cmdbuf.drawIndirectCount(buffer->Handle(), base, count_buffer->Handle(), count_base,
max_count, AmdGpu::Liverpool::DrawIndirectArgsSize);
} else {
cmdbuf.drawIndirect(buffer->Handle(), base, max_count,
AmdGpu::Liverpool::DrawIndirectArgsSize);
}
}
}

View file

@ -32,7 +32,8 @@ public:
}
void Draw(bool is_indexed, u32 index_offset = 0);
void DrawIndirect(bool is_indexed, VAddr address, u32 offset, u32 size);
void DrawIndirect(bool is_indexed, VAddr arg_address, u32 offset, u32 size, u32 max_count,
VAddr count_address);
void DispatchDirect();
void DispatchIndirect(VAddr address, u32 offset, u32 size);