mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-05-31 15:53:17 +00:00
Initial support of Geometry shaders (#1244)
* video_core: initial GS support * fix for components mapping; missing prim type
This commit is contained in:
psucien
GitHub
parent
5bb45dc7ba
commit
927bb0c175
40 changed files with 944 additions and 268 deletions
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@ -19,6 +19,7 @@
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#include "common/types.h"
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#include "common/unique_function.h"
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#include "shader_recompiler/params.h"
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#include "types.h"
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#include "video_core/amdgpu/pixel_format.h"
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#include "video_core/amdgpu/resource.h"
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@ -842,26 +843,6 @@ struct Liverpool {
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}
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};
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enum class PrimitiveType : u32 {
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None = 0,
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PointList = 1,
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LineList = 2,
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LineStrip = 3,
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TriangleList = 4,
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TriangleFan = 5,
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TriangleStrip = 6,
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PatchPrimitive = 9,
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AdjLineList = 10,
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AdjLineStrip = 11,
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AdjTriangleList = 12,
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AdjTriangleStrip = 13,
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RectList = 17,
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LineLoop = 18,
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QuadList = 19,
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QuadStrip = 20,
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Polygon = 21,
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};
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enum ContextRegs : u32 {
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DbZInfo = 0xA010,
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CbColor0Base = 0xA318,
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@ -936,7 +917,12 @@ struct Liverpool {
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};
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union ShaderStageEnable {
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u32 raw;
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enum VgtStages : u32 {
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Vs = 0u, // always enabled
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EsGs = 0xB0u,
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};
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VgtStages raw;
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BitField<0, 2, u32> ls_en;
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BitField<2, 1, u32> hs_en;
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BitField<3, 2, u32> es_en;
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@ -962,6 +948,81 @@ struct Liverpool {
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}
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};
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union GsInstances {
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u32 raw;
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struct {
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u32 enable : 2;
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u32 count : 6;
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};
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bool IsEnabled() const {
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return enable && count > 0;
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}
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};
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union GsOutPrimitiveType {
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u32 raw;
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struct {
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GsOutputPrimitiveType outprim_type : 6;
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GsOutputPrimitiveType outprim_type1 : 6;
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GsOutputPrimitiveType outprim_type2 : 6;
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GsOutputPrimitiveType outprim_type3 : 6;
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u32 reserved : 3;
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u32 unique_type_per_stream : 1;
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};
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GsOutputPrimitiveType GetPrimitiveType(u32 stream) const {
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if (unique_type_per_stream == 0) {
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return outprim_type;
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}
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switch (stream) {
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case 0:
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return outprim_type;
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case 1:
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return outprim_type1;
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case 2:
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return outprim_type2;
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case 3:
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return outprim_type3;
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default:
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UNREACHABLE();
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}
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}
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};
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union GsMode {
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u32 raw;
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BitField<0, 3, u32> mode;
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BitField<3, 2, u32> cut_mode;
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BitField<22, 2, u32> onchip;
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};
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union StreamOutConfig {
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u32 raw;
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struct {
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u32 streamout_0_en : 1;
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u32 streamout_1_en : 1;
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u32 streamout_2_en : 1;
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u32 streamout_3_en : 1;
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u32 rast_stream : 3;
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u32 : 1;
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u32 rast_stream_mask : 4;
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u32 : 19;
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u32 use_rast_stream_mask : 1;
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};
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};
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union StreamOutBufferConfig {
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u32 raw;
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struct {
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u32 stream_0_buf_en : 4;
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u32 stream_1_buf_en : 4;
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u32 stream_2_buf_en : 4;
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u32 stream_3_buf_en : 4;
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};
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};
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union Eqaa {
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u32 raw;
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BitField<0, 1, u32> max_anchor_samples;
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@ -1053,9 +1114,13 @@ struct Liverpool {
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PolygonControl polygon_control;
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ViewportControl viewport_control;
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VsOutputControl vs_output_control;
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INSERT_PADDING_WORDS(0xA292 - 0xA207 - 1);
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INSERT_PADDING_WORDS(0xA290 - 0xA207 - 1);
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GsMode vgt_gs_mode;
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INSERT_PADDING_WORDS(1);
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ModeControl mode_control;
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INSERT_PADDING_WORDS(0xA29D - 0xA292 - 1);
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INSERT_PADDING_WORDS(8);
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GsOutPrimitiveType vgt_gs_out_prim_type;
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INSERT_PADDING_WORDS(1);
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u32 index_size;
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u32 max_index_size;
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IndexBufferType index_buffer_type;
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@ -1066,11 +1131,21 @@ struct Liverpool {
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INSERT_PADDING_WORDS(0xA2A8 - 0xA2A5 - 1);
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u32 vgt_instance_step_rate_0;
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u32 vgt_instance_step_rate_1;
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INSERT_PADDING_WORDS(0xA2D5 - 0xA2A9 - 1);
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INSERT_PADDING_WORDS(0xA2AB - 0xA2A9 - 1);
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u32 vgt_esgs_ring_itemsize;
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u32 vgt_gsvs_ring_itemsize;
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INSERT_PADDING_WORDS(0xA2CE - 0xA2AC - 1);
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BitField<0, 11, u32> vgt_gs_max_vert_out;
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INSERT_PADDING_WORDS(0xA2D5 - 0xA2CE - 1);
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ShaderStageEnable stage_enable;
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INSERT_PADDING_WORDS(9);
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INSERT_PADDING_WORDS(1);
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u32 vgt_gs_vert_itemsize[4];
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INSERT_PADDING_WORDS(4);
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PolygonOffset poly_offset;
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INSERT_PADDING_WORDS(0xA2F8 - 0xA2DF - 5);
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GsInstances vgt_gs_instance_cnt;
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StreamOutConfig vgt_strmout_config;
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StreamOutBufferConfig vgt_strmout_buffer_config;
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INSERT_PADDING_WORDS(0xA2F8 - 0xA2E6 - 1);
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AaConfig aa_config;
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INSERT_PADDING_WORDS(0xA318 - 0xA2F8 - 1);
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ColorBuffer color_buffers[NumColorBuffers];
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@ -1291,15 +1366,24 @@ static_assert(GFX6_3D_REG_INDEX(color_control) == 0xA202);
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static_assert(GFX6_3D_REG_INDEX(clipper_control) == 0xA204);
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static_assert(GFX6_3D_REG_INDEX(viewport_control) == 0xA206);
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static_assert(GFX6_3D_REG_INDEX(vs_output_control) == 0xA207);
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static_assert(GFX6_3D_REG_INDEX(vgt_gs_mode) == 0xA290);
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static_assert(GFX6_3D_REG_INDEX(mode_control) == 0xA292);
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static_assert(GFX6_3D_REG_INDEX(vgt_gs_out_prim_type) == 0xA29B);
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static_assert(GFX6_3D_REG_INDEX(index_size) == 0xA29D);
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static_assert(GFX6_3D_REG_INDEX(index_buffer_type) == 0xA29F);
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static_assert(GFX6_3D_REG_INDEX(enable_primitive_id) == 0xA2A1);
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static_assert(GFX6_3D_REG_INDEX(enable_primitive_restart) == 0xA2A5);
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static_assert(GFX6_3D_REG_INDEX(vgt_instance_step_rate_0) == 0xA2A8);
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static_assert(GFX6_3D_REG_INDEX(vgt_instance_step_rate_1) == 0xA2A9);
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static_assert(GFX6_3D_REG_INDEX(vgt_esgs_ring_itemsize) == 0xA2AB);
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static_assert(GFX6_3D_REG_INDEX(vgt_gsvs_ring_itemsize) == 0xA2AC);
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static_assert(GFX6_3D_REG_INDEX(vgt_gs_max_vert_out) == 0xA2CE);
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static_assert(GFX6_3D_REG_INDEX(stage_enable) == 0xA2D5);
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static_assert(GFX6_3D_REG_INDEX(vgt_gs_vert_itemsize[0]) == 0xA2D7);
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static_assert(GFX6_3D_REG_INDEX(poly_offset) == 0xA2DF);
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static_assert(GFX6_3D_REG_INDEX(vgt_gs_instance_cnt) == 0xA2E4);
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static_assert(GFX6_3D_REG_INDEX(vgt_strmout_config) == 0xA2E5);
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static_assert(GFX6_3D_REG_INDEX(vgt_strmout_buffer_config) == 0xA2E6);
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static_assert(GFX6_3D_REG_INDEX(aa_config) == 0xA2F8);
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static_assert(GFX6_3D_REG_INDEX(color_buffers[0].base_address) == 0xA318);
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static_assert(GFX6_3D_REG_INDEX(color_buffers[0].pitch) == 0xA319);
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@ -6,78 +6,10 @@
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#include <string_view>
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#include <fmt/format.h>
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#include "common/types.h"
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#include "video_core/amdgpu/types.h"
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namespace AmdGpu {
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// Table 8.13 Data and Image Formats [Sea Islands Series Instruction Set Architecture]
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enum class DataFormat : u32 {
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FormatInvalid = 0,
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Format8 = 1,
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Format16 = 2,
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Format8_8 = 3,
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Format32 = 4,
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Format16_16 = 5,
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Format10_11_11 = 6,
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Format11_11_10 = 7,
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Format10_10_10_2 = 8,
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Format2_10_10_10 = 9,
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Format8_8_8_8 = 10,
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Format32_32 = 11,
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Format16_16_16_16 = 12,
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Format32_32_32 = 13,
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Format32_32_32_32 = 14,
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Format5_6_5 = 16,
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Format1_5_5_5 = 17,
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Format5_5_5_1 = 18,
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Format4_4_4_4 = 19,
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Format8_24 = 20,
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Format24_8 = 21,
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FormatX24_8_32 = 22,
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FormatGB_GR = 32,
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FormatBG_RG = 33,
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Format5_9_9_9 = 34,
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FormatBc1 = 35,
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FormatBc2 = 36,
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FormatBc3 = 37,
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FormatBc4 = 38,
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FormatBc5 = 39,
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FormatBc6 = 40,
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FormatBc7 = 41,
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FormatFmask8_1 = 47,
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FormatFmask8_2 = 48,
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FormatFmask8_4 = 49,
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FormatFmask16_1 = 50,
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FormatFmask16_2 = 51,
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FormatFmask32_2 = 52,
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FormatFmask32_4 = 53,
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FormatFmask32_8 = 54,
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FormatFmask64_4 = 55,
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FormatFmask64_8 = 56,
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Format4_4 = 57,
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Format6_5_5 = 58,
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Format1 = 59,
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Format1_Reversed = 60,
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Format32_As_8 = 61,
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Format32_As_8_8 = 62,
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Format32_As_32_32_32_32 = 63,
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};
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enum class NumberFormat : u32 {
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Unorm = 0,
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Snorm = 1,
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Uscaled = 2,
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Sscaled = 3,
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Uint = 4,
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Sint = 5,
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SnormNz = 6,
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Float = 7,
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Srgb = 9,
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Ubnorm = 10,
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UbnromNz = 11,
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Ubint = 12,
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Ubscaled = 13,
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};
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[[nodiscard]] constexpr bool IsInteger(NumberFormat nfmt) {
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return nfmt == AmdGpu::NumberFormat::Sint || nfmt == AmdGpu::NumberFormat::Uint;
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}
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106
src/video_core/amdgpu/types.h
Normal file
106
src/video_core/amdgpu/types.h
Normal file
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@ -0,0 +1,106 @@
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include "common/types.h"
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namespace AmdGpu {
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// See `VGT_PRIMITIVE_TYPE` description in [Radeon Sea Islands 3D/Compute Register Reference Guide]
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enum class PrimitiveType : u32 {
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None = 0,
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PointList = 1,
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LineList = 2,
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LineStrip = 3,
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TriangleList = 4,
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TriangleFan = 5,
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TriangleStrip = 6,
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PatchPrimitive = 9,
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AdjLineList = 10,
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AdjLineStrip = 11,
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AdjTriangleList = 12,
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AdjTriangleStrip = 13,
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RectList = 17,
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LineLoop = 18,
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QuadList = 19,
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QuadStrip = 20,
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Polygon = 21,
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};
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enum class GsOutputPrimitiveType : u32 {
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PointList = 0,
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LineStrip = 1,
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TriangleStrip = 2,
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};
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// Table 8.13 Data and Image Formats [Sea Islands Series Instruction Set Architecture]
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enum class DataFormat : u32 {
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FormatInvalid = 0,
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Format8 = 1,
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Format16 = 2,
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Format8_8 = 3,
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Format32 = 4,
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Format16_16 = 5,
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Format10_11_11 = 6,
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Format11_11_10 = 7,
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Format10_10_10_2 = 8,
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Format2_10_10_10 = 9,
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Format8_8_8_8 = 10,
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Format32_32 = 11,
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Format16_16_16_16 = 12,
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Format32_32_32 = 13,
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Format32_32_32_32 = 14,
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Format5_6_5 = 16,
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Format1_5_5_5 = 17,
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Format5_5_5_1 = 18,
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Format4_4_4_4 = 19,
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Format8_24 = 20,
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Format24_8 = 21,
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FormatX24_8_32 = 22,
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FormatGB_GR = 32,
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FormatBG_RG = 33,
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Format5_9_9_9 = 34,
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FormatBc1 = 35,
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FormatBc2 = 36,
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FormatBc3 = 37,
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FormatBc4 = 38,
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FormatBc5 = 39,
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FormatBc6 = 40,
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FormatBc7 = 41,
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FormatFmask8_1 = 47,
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FormatFmask8_2 = 48,
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FormatFmask8_4 = 49,
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FormatFmask16_1 = 50,
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FormatFmask16_2 = 51,
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FormatFmask32_2 = 52,
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FormatFmask32_4 = 53,
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FormatFmask32_8 = 54,
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FormatFmask64_4 = 55,
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FormatFmask64_8 = 56,
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Format4_4 = 57,
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Format6_5_5 = 58,
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Format1 = 59,
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Format1_Reversed = 60,
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Format32_As_8 = 61,
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Format32_As_8_8 = 62,
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Format32_As_32_32_32_32 = 63,
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};
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enum class NumberFormat : u32 {
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Unorm = 0,
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Snorm = 1,
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Uscaled = 2,
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Sscaled = 3,
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Uint = 4,
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Sint = 5,
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SnormNz = 6,
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Float = 7,
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Srgb = 9,
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Ubnorm = 10,
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UbnromNz = 11,
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Ubint = 12,
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Ubscaled = 13,
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};
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} // namespace AmdGpu
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@ -224,7 +224,7 @@ bool BufferCache::BindVertexBuffers(const Shader::Info& vs_info) {
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u32 BufferCache::BindIndexBuffer(bool& is_indexed, u32 index_offset) {
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// Emulate QuadList primitive type with CPU made index buffer.
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const auto& regs = liverpool->regs;
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if (regs.primitive_type == AmdGpu::Liverpool::PrimitiveType::QuadList) {
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if (regs.primitive_type == AmdGpu::PrimitiveType::QuadList) {
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is_indexed = true;
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// Emit indices.
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@ -61,34 +61,34 @@ vk::CompareOp CompareOp(Liverpool::CompareFunc func) {
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}
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}
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vk::PrimitiveTopology PrimitiveType(Liverpool::PrimitiveType type) {
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vk::PrimitiveTopology PrimitiveType(AmdGpu::PrimitiveType type) {
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switch (type) {
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case Liverpool::PrimitiveType::PointList:
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case AmdGpu::PrimitiveType::PointList:
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return vk::PrimitiveTopology::ePointList;
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case Liverpool::PrimitiveType::LineList:
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case AmdGpu::PrimitiveType::LineList:
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return vk::PrimitiveTopology::eLineList;
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case Liverpool::PrimitiveType::LineStrip:
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case AmdGpu::PrimitiveType::LineStrip:
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return vk::PrimitiveTopology::eLineStrip;
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case Liverpool::PrimitiveType::TriangleList:
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case AmdGpu::PrimitiveType::TriangleList:
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return vk::PrimitiveTopology::eTriangleList;
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case Liverpool::PrimitiveType::TriangleFan:
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case AmdGpu::PrimitiveType::TriangleFan:
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return vk::PrimitiveTopology::eTriangleFan;
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case Liverpool::PrimitiveType::TriangleStrip:
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case AmdGpu::PrimitiveType::TriangleStrip:
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return vk::PrimitiveTopology::eTriangleStrip;
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case Liverpool::PrimitiveType::AdjLineList:
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case AmdGpu::PrimitiveType::AdjLineList:
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return vk::PrimitiveTopology::eLineListWithAdjacency;
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case Liverpool::PrimitiveType::AdjLineStrip:
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case AmdGpu::PrimitiveType::AdjLineStrip:
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return vk::PrimitiveTopology::eLineStripWithAdjacency;
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case Liverpool::PrimitiveType::AdjTriangleList:
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case AmdGpu::PrimitiveType::AdjTriangleList:
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return vk::PrimitiveTopology::eTriangleListWithAdjacency;
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case Liverpool::PrimitiveType::AdjTriangleStrip:
|
||||
case AmdGpu::PrimitiveType::AdjTriangleStrip:
|
||||
return vk::PrimitiveTopology::eTriangleStripWithAdjacency;
|
||||
case Liverpool::PrimitiveType::PatchPrimitive:
|
||||
case AmdGpu::PrimitiveType::PatchPrimitive:
|
||||
return vk::PrimitiveTopology::ePatchList;
|
||||
case Liverpool::PrimitiveType::QuadList:
|
||||
case AmdGpu::PrimitiveType::QuadList:
|
||||
// Needs to generate index buffer on the fly.
|
||||
return vk::PrimitiveTopology::eTriangleList;
|
||||
case Liverpool::PrimitiveType::RectList:
|
||||
case AmdGpu::PrimitiveType::RectList:
|
||||
return vk::PrimitiveTopology::eTriangleStrip;
|
||||
default:
|
||||
UNREACHABLE();
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ vk::StencilOp StencilOp(Liverpool::StencilFunc op);
|
|||
|
||||
vk::CompareOp CompareOp(Liverpool::CompareFunc func);
|
||||
|
||||
vk::PrimitiveTopology PrimitiveType(Liverpool::PrimitiveType type);
|
||||
vk::PrimitiveTopology PrimitiveType(AmdGpu::PrimitiveType type);
|
||||
|
||||
vk::PolygonMode PolygonMode(Liverpool::PolygonMode mode);
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,10 @@
|
|||
|
||||
namespace Vulkan {
|
||||
|
||||
static constexpr auto gp_stage_flags = vk::ShaderStageFlagBits::eVertex |
|
||||
vk::ShaderStageFlagBits::eGeometry |
|
||||
vk::ShaderStageFlagBits::eFragment;
|
||||
|
||||
GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& scheduler_,
|
||||
DescriptorHeap& desc_heap_, const GraphicsPipelineKey& key_,
|
||||
vk::PipelineCache pipeline_cache,
|
||||
|
|
@ -27,7 +31,7 @@ GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& schedul
|
|||
BuildDescSetLayout();
|
||||
|
||||
const vk::PushConstantRange push_constants = {
|
||||
.stageFlags = vk::ShaderStageFlagBits::eVertex | vk::ShaderStageFlagBits::eFragment,
|
||||
.stageFlags = gp_stage_flags,
|
||||
.offset = 0,
|
||||
.size = sizeof(Shader::PushData),
|
||||
};
|
||||
|
|
@ -83,7 +87,7 @@ GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& schedul
|
|||
.pVertexAttributeDescriptions = vertex_attributes.data(),
|
||||
};
|
||||
|
||||
if (key.prim_type == Liverpool::PrimitiveType::RectList && !IsEmbeddedVs()) {
|
||||
if (key.prim_type == AmdGpu::PrimitiveType::RectList && !IsEmbeddedVs()) {
|
||||
LOG_WARNING(Render_Vulkan,
|
||||
"Rectangle List primitive type is only supported for embedded VS");
|
||||
}
|
||||
|
|
@ -196,9 +200,9 @@ GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& schedul
|
|||
},
|
||||
};
|
||||
|
||||
auto stage = u32(Shader::Stage::Vertex);
|
||||
boost::container::static_vector<vk::PipelineShaderStageCreateInfo, MaxShaderStages>
|
||||
shader_stages;
|
||||
auto stage = u32(Shader::Stage::Vertex);
|
||||
if (infos[stage]) {
|
||||
shader_stages.emplace_back(vk::PipelineShaderStageCreateInfo{
|
||||
.stage = vk::ShaderStageFlagBits::eVertex,
|
||||
|
|
@ -206,6 +210,14 @@ GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& schedul
|
|||
.pName = "main",
|
||||
});
|
||||
}
|
||||
stage = u32(Shader::Stage::Geometry);
|
||||
if (infos[stage]) {
|
||||
shader_stages.emplace_back(vk::PipelineShaderStageCreateInfo{
|
||||
.stage = vk::ShaderStageFlagBits::eGeometry,
|
||||
.module = modules[stage],
|
||||
.pName = "main",
|
||||
});
|
||||
}
|
||||
stage = u32(Shader::Stage::Fragment);
|
||||
if (infos[stage]) {
|
||||
shader_stages.emplace_back(vk::PipelineShaderStageCreateInfo{
|
||||
|
|
@ -322,7 +334,7 @@ void GraphicsPipeline::BuildDescSetLayout() {
|
|||
.descriptorType = buffer.IsStorage(sharp) ? vk::DescriptorType::eStorageBuffer
|
||||
: vk::DescriptorType::eUniformBuffer,
|
||||
.descriptorCount = 1,
|
||||
.stageFlags = vk::ShaderStageFlagBits::eVertex | vk::ShaderStageFlagBits::eFragment,
|
||||
.stageFlags = gp_stage_flags,
|
||||
});
|
||||
}
|
||||
for (const auto& tex_buffer : stage->texture_buffers) {
|
||||
|
|
@ -331,7 +343,7 @@ void GraphicsPipeline::BuildDescSetLayout() {
|
|||
.descriptorType = tex_buffer.is_written ? vk::DescriptorType::eStorageTexelBuffer
|
||||
: vk::DescriptorType::eUniformTexelBuffer,
|
||||
.descriptorCount = 1,
|
||||
.stageFlags = vk::ShaderStageFlagBits::eVertex | vk::ShaderStageFlagBits::eFragment,
|
||||
.stageFlags = gp_stage_flags,
|
||||
});
|
||||
}
|
||||
for (const auto& image : stage->images) {
|
||||
|
|
@ -340,7 +352,7 @@ void GraphicsPipeline::BuildDescSetLayout() {
|
|||
.descriptorType = image.is_storage ? vk::DescriptorType::eStorageImage
|
||||
: vk::DescriptorType::eSampledImage,
|
||||
.descriptorCount = 1,
|
||||
.stageFlags = vk::ShaderStageFlagBits::eVertex | vk::ShaderStageFlagBits::eFragment,
|
||||
.stageFlags = gp_stage_flags,
|
||||
});
|
||||
}
|
||||
for (const auto& sampler : stage->samplers) {
|
||||
|
|
@ -348,7 +360,7 @@ void GraphicsPipeline::BuildDescSetLayout() {
|
|||
.binding = binding++,
|
||||
.descriptorType = vk::DescriptorType::eSampler,
|
||||
.descriptorCount = 1,
|
||||
.stageFlags = vk::ShaderStageFlagBits::eVertex | vk::ShaderStageFlagBits::eFragment,
|
||||
.stageFlags = gp_stage_flags,
|
||||
});
|
||||
}
|
||||
}
|
||||
|
|
@ -518,9 +530,7 @@ void GraphicsPipeline::BindResources(const Liverpool::Regs& regs,
|
|||
desc_set, {});
|
||||
}
|
||||
}
|
||||
cmdbuf.pushConstants(*pipeline_layout,
|
||||
vk::ShaderStageFlagBits::eVertex | vk::ShaderStageFlagBits::eFragment, 0U,
|
||||
sizeof(push_data), &push_data);
|
||||
cmdbuf.pushConstants(*pipeline_layout, gp_stage_flags, 0U, sizeof(push_data), &push_data);
|
||||
cmdbuf.bindPipeline(vk::PipelineBindPoint::eGraphics, Handle());
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ struct GraphicsPipelineKey {
|
|||
u32 num_samples;
|
||||
u32 mrt_mask;
|
||||
Liverpool::StencilControl stencil;
|
||||
Liverpool::PrimitiveType prim_type;
|
||||
AmdGpu::PrimitiveType prim_type;
|
||||
u32 enable_primitive_restart;
|
||||
u32 primitive_restart_index;
|
||||
Liverpool::PolygonMode polygon_mode;
|
||||
|
|
@ -86,13 +86,13 @@ public:
|
|||
}
|
||||
|
||||
[[nodiscard]] bool IsPrimitiveListTopology() const {
|
||||
return key.prim_type == Liverpool::PrimitiveType::PointList ||
|
||||
key.prim_type == Liverpool::PrimitiveType::LineList ||
|
||||
key.prim_type == Liverpool::PrimitiveType::TriangleList ||
|
||||
key.prim_type == Liverpool::PrimitiveType::AdjLineList ||
|
||||
key.prim_type == Liverpool::PrimitiveType::AdjTriangleList ||
|
||||
key.prim_type == Liverpool::PrimitiveType::RectList ||
|
||||
key.prim_type == Liverpool::PrimitiveType::QuadList;
|
||||
return key.prim_type == AmdGpu::PrimitiveType::PointList ||
|
||||
key.prim_type == AmdGpu::PrimitiveType::LineList ||
|
||||
key.prim_type == AmdGpu::PrimitiveType::TriangleList ||
|
||||
key.prim_type == AmdGpu::PrimitiveType::AdjLineList ||
|
||||
key.prim_type == AmdGpu::PrimitiveType::AdjTriangleList ||
|
||||
key.prim_type == AmdGpu::PrimitiveType::RectList ||
|
||||
key.prim_type == AmdGpu::PrimitiveType::QuadList;
|
||||
}
|
||||
|
||||
private:
|
||||
|
|
|
|||
|
|
@ -322,6 +322,7 @@ bool Instance::CreateDevice() {
|
|||
.geometryShader = features.geometryShader,
|
||||
.logicOp = features.logicOp,
|
||||
.depthBiasClamp = features.depthBiasClamp,
|
||||
.fillModeNonSolid = features.fillModeNonSolid,
|
||||
.multiViewport = features.multiViewport,
|
||||
.samplerAnisotropy = features.samplerAnisotropy,
|
||||
.vertexPipelineStoresAndAtomics = features.vertexPipelineStoresAndAtomics,
|
||||
|
|
|
|||
|
|
@ -147,6 +147,16 @@ public:
|
|||
return list_restart;
|
||||
}
|
||||
|
||||
/// Returns true when geometry shaders are supported by the device
|
||||
bool IsGeometryStageSupported() const {
|
||||
return features.geometryShader;
|
||||
}
|
||||
|
||||
/// Returns true when tessellation is supported by the device
|
||||
bool IsTessellationSupported() const {
|
||||
return features.tessellationShader;
|
||||
}
|
||||
|
||||
/// Returns the vendor ID of the physical device
|
||||
u32 GetVendorID() const {
|
||||
return properties.vendorID;
|
||||
|
|
|
|||
|
|
@ -7,7 +7,10 @@
|
|||
#include "common/io_file.h"
|
||||
#include "common/path_util.h"
|
||||
#include "shader_recompiler/backend/spirv/emit_spirv.h"
|
||||
#include "shader_recompiler/frontend/copy_shader.h"
|
||||
#include "shader_recompiler/info.h"
|
||||
#include "shader_recompiler/recompiler.h"
|
||||
#include "shader_recompiler/runtime_info.h"
|
||||
#include "video_core/renderer_vulkan/renderer_vulkan.h"
|
||||
#include "video_core/renderer_vulkan/vk_instance.h"
|
||||
#include "video_core/renderer_vulkan/vk_pipeline_cache.h"
|
||||
|
|
@ -82,6 +85,13 @@ Shader::RuntimeInfo PipelineCache::BuildRuntimeInfo(Shader::Stage stage) {
|
|||
auto info = Shader::RuntimeInfo{stage};
|
||||
const auto& regs = liverpool->regs;
|
||||
switch (stage) {
|
||||
case Shader::Stage::Export: {
|
||||
info.num_user_data = regs.es_program.settings.num_user_regs;
|
||||
info.num_input_vgprs = regs.es_program.settings.vgpr_comp_cnt;
|
||||
info.num_allocated_vgprs = regs.es_program.settings.num_vgprs * 4;
|
||||
info.es_info.vertex_data_size = regs.vgt_esgs_ring_itemsize;
|
||||
break;
|
||||
}
|
||||
case Shader::Stage::Vertex: {
|
||||
info.num_user_data = regs.vs_program.settings.num_user_regs;
|
||||
info.num_input_vgprs = regs.vs_program.settings.vgpr_comp_cnt;
|
||||
|
|
@ -92,6 +102,29 @@ Shader::RuntimeInfo PipelineCache::BuildRuntimeInfo(Shader::Stage stage) {
|
|||
regs.clipper_control.clip_space == Liverpool::ClipSpace::MinusWToW;
|
||||
break;
|
||||
}
|
||||
case Shader::Stage::Geometry: {
|
||||
info.num_user_data = regs.gs_program.settings.num_user_regs;
|
||||
info.num_input_vgprs = regs.gs_program.settings.vgpr_comp_cnt;
|
||||
info.num_allocated_vgprs = regs.gs_program.settings.num_vgprs * 4;
|
||||
info.gs_info.output_vertices = regs.vgt_gs_max_vert_out;
|
||||
info.gs_info.num_invocations =
|
||||
regs.vgt_gs_instance_cnt.IsEnabled() ? regs.vgt_gs_instance_cnt.count : 1;
|
||||
info.gs_info.in_primitive = regs.primitive_type;
|
||||
for (u32 stream_id = 0; stream_id < Shader::GsMaxOutputStreams; ++stream_id) {
|
||||
info.gs_info.out_primitive[stream_id] =
|
||||
regs.vgt_gs_out_prim_type.GetPrimitiveType(stream_id);
|
||||
}
|
||||
info.gs_info.in_vertex_data_size = regs.vgt_esgs_ring_itemsize;
|
||||
info.gs_info.out_vertex_data_size = regs.vgt_gs_vert_itemsize[0];
|
||||
|
||||
// Extract semantics offsets from a copy shader
|
||||
const auto vc_stage = Shader::Stage::Vertex;
|
||||
const auto* pgm_vc = regs.ProgramForStage(static_cast<u32>(vc_stage));
|
||||
const auto params_vc = Liverpool::GetParams(*pgm_vc);
|
||||
DumpShader(params_vc.code, params_vc.hash, Shader::Stage::Vertex, 0, "copy.bin");
|
||||
info.gs_info.copy_data = Shader::ParseCopyShader(params_vc.code);
|
||||
break;
|
||||
}
|
||||
case Shader::Stage::Fragment: {
|
||||
info.num_user_data = regs.ps_program.settings.num_user_regs;
|
||||
info.num_allocated_vgprs = regs.ps_program.settings.num_vgprs * 4;
|
||||
|
|
@ -149,7 +182,7 @@ PipelineCache::~PipelineCache() = default;
|
|||
const GraphicsPipeline* PipelineCache::GetGraphicsPipeline() {
|
||||
const auto& regs = liverpool->regs;
|
||||
// Tessellation is unsupported so skip the draw to avoid locking up the driver.
|
||||
if (regs.primitive_type == Liverpool::PrimitiveType::PatchPrimitive) {
|
||||
if (regs.primitive_type == AmdGpu::PrimitiveType::PatchPrimitive) {
|
||||
return nullptr;
|
||||
}
|
||||
// There are several cases (e.g. FCE, FMask/HTile decompression) where we don't need to do an
|
||||
|
|
@ -163,7 +196,7 @@ const GraphicsPipeline* PipelineCache::GetGraphicsPipeline() {
|
|||
LOG_TRACE(Render_Vulkan, "FMask decompression pass skipped");
|
||||
return nullptr;
|
||||
}
|
||||
if (regs.primitive_type == Liverpool::PrimitiveType::None) {
|
||||
if (regs.primitive_type == AmdGpu::PrimitiveType::None) {
|
||||
LOG_TRACE(Render_Vulkan, "Primitive type 'None' skipped");
|
||||
return nullptr;
|
||||
}
|
||||
|
|
@ -190,15 +223,6 @@ const ComputePipeline* PipelineCache::GetComputePipeline() {
|
|||
return it->second;
|
||||
}
|
||||
|
||||
bool ShouldSkipShader(u64 shader_hash, const char* shader_type) {
|
||||
static constexpr std::array<u64, 0> skip_hashes = {};
|
||||
if (std::ranges::contains(skip_hashes, shader_hash)) {
|
||||
LOG_WARNING(Render_Vulkan, "Skipped {} shader hash {:#x}.", shader_type, shader_hash);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool PipelineCache::RefreshGraphicsKey() {
|
||||
std::memset(&graphics_key, 0, sizeof(GraphicsPipelineKey));
|
||||
|
||||
|
|
@ -275,46 +299,66 @@ bool PipelineCache::RefreshGraphicsKey() {
|
|||
}
|
||||
|
||||
Shader::Backend::Bindings binding{};
|
||||
for (u32 i = 0; i < MaxShaderStages; i++) {
|
||||
if (!regs.stage_enable.IsStageEnabled(i)) {
|
||||
key.stage_hashes[i] = 0;
|
||||
infos[i] = nullptr;
|
||||
continue;
|
||||
const auto& TryBindStageRemap = [&](Shader::Stage stage_in, Shader::Stage stage_out) -> bool {
|
||||
const auto stage_in_idx = static_cast<u32>(stage_in);
|
||||
const auto stage_out_idx = static_cast<u32>(stage_out);
|
||||
if (!regs.stage_enable.IsStageEnabled(stage_in_idx)) {
|
||||
key.stage_hashes[stage_out_idx] = 0;
|
||||
infos[stage_out_idx] = nullptr;
|
||||
return false;
|
||||
}
|
||||
auto* pgm = regs.ProgramForStage(i);
|
||||
|
||||
const auto* pgm = regs.ProgramForStage(stage_in_idx);
|
||||
if (!pgm || !pgm->Address<u32*>()) {
|
||||
key.stage_hashes[i] = 0;
|
||||
infos[i] = nullptr;
|
||||
continue;
|
||||
key.stage_hashes[stage_out_idx] = 0;
|
||||
infos[stage_out_idx] = nullptr;
|
||||
return false;
|
||||
}
|
||||
|
||||
const auto* bininfo = Liverpool::GetBinaryInfo(*pgm);
|
||||
if (!bininfo->Valid()) {
|
||||
LOG_WARNING(Render_Vulkan, "Invalid binary info structure!");
|
||||
key.stage_hashes[i] = 0;
|
||||
infos[i] = nullptr;
|
||||
continue;
|
||||
}
|
||||
if (ShouldSkipShader(bininfo->shader_hash, "graphics")) {
|
||||
return false;
|
||||
}
|
||||
const auto stage = Shader::StageFromIndex(i);
|
||||
const auto params = Liverpool::GetParams(*pgm);
|
||||
|
||||
if (stage != Shader::Stage::Vertex && stage != Shader::Stage::Fragment) {
|
||||
key.stage_hashes[stage_out_idx] = 0;
|
||||
infos[stage_out_idx] = nullptr;
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool TessMissingLogged = false;
|
||||
if (auto* pgm = regs.ProgramForStage(3);
|
||||
regs.stage_enable.IsStageEnabled(3) && pgm->Address() != 0) {
|
||||
if (!TessMissingLogged) {
|
||||
LOG_WARNING(Render_Vulkan, "Tess pipeline compilation skipped");
|
||||
TessMissingLogged = true;
|
||||
}
|
||||
auto params = Liverpool::GetParams(*pgm);
|
||||
std::tie(infos[stage_out_idx], modules[stage_out_idx], key.stage_hashes[stage_out_idx]) =
|
||||
GetProgram(stage_in, params, binding);
|
||||
return true;
|
||||
};
|
||||
|
||||
const auto& TryBindStage = [&](Shader::Stage stage) { return TryBindStageRemap(stage, stage); };
|
||||
|
||||
const auto& IsGsFeaturesSupported = [&]() -> bool {
|
||||
// These checks are temporary until all functionality is implemented.
|
||||
return !regs.vgt_gs_mode.onchip && !regs.vgt_strmout_config.raw;
|
||||
};
|
||||
|
||||
TryBindStage(Shader::Stage::Fragment);
|
||||
|
||||
const auto* fs_info = infos[static_cast<u32>(Shader::Stage::Fragment)];
|
||||
key.mrt_mask = fs_info ? fs_info->mrt_mask : 0u;
|
||||
|
||||
switch (regs.stage_enable.raw) {
|
||||
case Liverpool::ShaderStageEnable::VgtStages::EsGs: {
|
||||
if (!instance.IsGeometryStageSupported() || !IsGsFeaturesSupported()) {
|
||||
break;
|
||||
}
|
||||
if (!TryBindStageRemap(Shader::Stage::Export, Shader::Stage::Vertex)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
std::tie(infos[i], modules[i], key.stage_hashes[i]) = GetProgram(stage, params, binding);
|
||||
if (!TryBindStage(Shader::Stage::Geometry)) {
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
}
|
||||
default: {
|
||||
TryBindStage(Shader::Stage::Vertex);
|
||||
infos[static_cast<u32>(Shader::Stage::Geometry)] = nullptr;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
const auto* vs_info = infos[static_cast<u32>(Shader::Stage::Vertex)];
|
||||
|
|
@ -336,9 +380,6 @@ bool PipelineCache::RefreshGraphicsKey() {
|
|||
}
|
||||
}
|
||||
|
||||
const auto* fs_info = infos[static_cast<u32>(Shader::Stage::Fragment)];
|
||||
key.mrt_mask = fs_info ? fs_info->mrt_mask : 0u;
|
||||
|
||||
// Second pass to fill remain CB pipeline key data
|
||||
for (auto cb = 0u, remapped_cb = 0u; cb < Liverpool::NumColorBuffers; ++cb) {
|
||||
auto const& col_buf = regs.color_buffers[cb];
|
||||
|
|
@ -364,9 +405,6 @@ bool PipelineCache::RefreshComputeKey() {
|
|||
Shader::Backend::Bindings binding{};
|
||||
const auto* cs_pgm = &liverpool->regs.cs_program;
|
||||
const auto cs_params = Liverpool::GetParams(*cs_pgm);
|
||||
if (ShouldSkipShader(cs_params.hash, "compute")) {
|
||||
return false;
|
||||
}
|
||||
std::tie(infos[0], modules[0], compute_key) =
|
||||
GetProgram(Shader::Stage::Compute, cs_params, binding);
|
||||
return true;
|
||||
|
|
@ -378,15 +416,11 @@ vk::ShaderModule PipelineCache::CompileModule(Shader::Info& info,
|
|||
Shader::Backend::Bindings& binding) {
|
||||
LOG_INFO(Render_Vulkan, "Compiling {} shader {:#x} {}", info.stage, info.pgm_hash,
|
||||
perm_idx != 0 ? "(permutation)" : "");
|
||||
if (Config::dumpShaders()) {
|
||||
DumpShader(code, info.pgm_hash, info.stage, perm_idx, "bin");
|
||||
}
|
||||
DumpShader(code, info.pgm_hash, info.stage, perm_idx, "bin");
|
||||
|
||||
const auto ir_program = Shader::TranslateProgram(code, pools, info, runtime_info, profile);
|
||||
const auto spv = Shader::Backend::SPIRV::EmitSPIRV(profile, runtime_info, ir_program, binding);
|
||||
if (Config::dumpShaders()) {
|
||||
DumpShader(spv, info.pgm_hash, info.stage, perm_idx, "spv");
|
||||
}
|
||||
DumpShader(spv, info.pgm_hash, info.stage, perm_idx, "spv");
|
||||
|
||||
const auto module = CompileSPV(spv, instance.GetDevice());
|
||||
const auto name = fmt::format("{}_{:#x}_{}", info.stage, info.pgm_hash, perm_idx);
|
||||
|
|
@ -429,6 +463,10 @@ std::tuple<const Shader::Info*, vk::ShaderModule, u64> PipelineCache::GetProgram
|
|||
|
||||
void PipelineCache::DumpShader(std::span<const u32> code, u64 hash, Shader::Stage stage,
|
||||
size_t perm_idx, std::string_view ext) {
|
||||
if (!Config::dumpShaders()) {
|
||||
return;
|
||||
}
|
||||
|
||||
using namespace Common::FS;
|
||||
const auto dump_dir = GetUserPath(PathType::ShaderDir) / "dumps";
|
||||
if (!std::filesystem::exists(dump_dir)) {
|
||||
|
|
|
|||
|
|
@ -70,9 +70,8 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
|
|||
cmdbuf.drawIndexed(num_indices, regs.num_instances.NumInstances(), 0, s32(vertex_offset),
|
||||
instance_offset);
|
||||
} else {
|
||||
const u32 num_vertices = regs.primitive_type == AmdGpu::Liverpool::PrimitiveType::RectList
|
||||
? 4
|
||||
: regs.num_indices;
|
||||
const u32 num_vertices =
|
||||
regs.primitive_type == AmdGpu::PrimitiveType::RectList ? 4 : regs.num_indices;
|
||||
cmdbuf.draw(num_vertices, regs.num_instances.NumInstances(), vertex_offset,
|
||||
instance_offset);
|
||||
}
|
||||
|
|
@ -88,7 +87,7 @@ void Rasterizer::DrawIndirect(bool is_indexed, VAddr address, u32 offset, u32 si
|
|||
return;
|
||||
}
|
||||
|
||||
ASSERT_MSG(regs.primitive_type != AmdGpu::Liverpool::PrimitiveType::RectList,
|
||||
ASSERT_MSG(regs.primitive_type != AmdGpu::PrimitiveType::RectList,
|
||||
"Unsupported primitive type for indirect draw");
|
||||
|
||||
try {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue